Semiconductor memory device with plural memory die and controller die
View Patent ↗A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.
1. A semiconductor memory device, including:
a plurality of memory die;
a controller die connected to an internal control bus, the controller die being configured to provide a selected one of the memory die with an internal read command in response to an external read command, the controller die comprising a master delay locked loop (DLL) to reference an internal clock signal to a global clock signal;
wherein the selected memory die is configured to provide read data to the controller die in response to the internal read command;
wherein a first latency between receipt by the controller die of the internal read command and receipt by the controller die of the read data from the selected memory die differs for at least two of the memory dies, the first latency differing depending on which of the at least two dies is selected as the selected memory die;
the controller die being further configured to output the received read data onto an external data bus, wherein a second latency between receipt by the controller die of the external read command and output of the read data onto the external data bus is uniform for said at least two o the memory dies when selected as the selected memory die.
2. The device of claim 1 , the controller die further configured to add an equalizing delay to the received read data after receipt from the selected memory die.
3. The device of claim 2 , wherein said latency between receipt by the controller die of the external read command and output of the read data onto the external data bus, which is uniform for said at least two of the memory dies, is a total overall latency, and wherein the equalizing delay is selected so as to ensure that the total overall latency is a deterministic number of clock cycles.
4. The device of claim 1 , the controller configured to select a first one of the memory dies as the selected memory die, to receive first read data from the first memory die, to select a second one of the memory dies as the selected memory die, to receive second read data from the second memory die and to output the first read data and the second read data onto an external data bus.
5. The device of claim 4 , wherein receipt of a terminal portion of the first read data occurs contemporaneously with receipt of an initial portion of the second read data and wherein the controller die is further configured to buffer at least said initial portion of the second read data so as to allow said initial portion of the second read data to be output onto the external data bus following said terminal portion of the first data.
6. The device of claim 4 , wherein a gap exists between receipt of a terminal portion of the first read data and receipt of an initial portion of the second read data, and wherein the controller die is further configured to delay outputting of the first read data so as to allow said initial portion of the second data to gaplessly follow said terminal portion of the first data on the external data bus.
7. The device of claim 1 , the memory dies including the selected memory die each including a respective internal data bus independently connecting the respective memory die to the controller die.
8. The device of claim 7 , the selected memory configured to provide the read data to the controller die by outputting the read data onto the respective internal data bus.
9. The device of claim 8 , the controller die further configured to disable the internal data bus of each of the memory die other than the selected memory die when receiving the read data output by the selected memory die.
10. The device of claim 1 , wherein the selected memory die lacks circuitry configured for providing on-die termination of the internal data and control busses.
11. The device of claim 7 , wherein the selected memory die includes circuitry configured for providing on-die termination of the internal data and control busses, but where said circuitry is disabled.
12. The device of claim 11 , wherein the selected memory die is configured with the on-die termination switched off.
13. The device of claim 1 , the controller die further configured to receive a global clock signal on an external control bus.
14. The device of claim 13 , wherein the controller die re-synchronizes the read data received from the selected memory die with the global clock signal.
15. The device of claim 1 , the controller die further configured to output the received read data onto an external data bus, wherein the external data bus and the internal data bus have the same width.
16. The device of claim 1 , the controller die further configured to output the received read data onto an external data bus, wherein the external data bus and the internal data bus have a different width.
17. The device of claim 1 , the controller die further configured to output the received read data onto an external data bus, wherein the internal data bus carries the read data from the selected memory die at a rate of N1 bits per second per conductor and wherein the external data bus carries the re-synchronized captured read data from the controller die at a rate of N2 bits per second per conductor, wherein N1 and N2 are the same.
18. The device of claim 1 , the controller die further configured to output the received read data onto an external data bus, wherein the internal data bus carries the read data from the selected memory die at a rate of N1 bits per second per conductor and wherein the external data bus carries the re-synchronized captured read data from the controller die at a rate of N2 bits per second per conductor, wherein N1 and N2 are different.
19. The device of claim 1 , the controller die further configured to output the received read data onto an external data bus, the controller die including termination circuitry configured for providing on-die termination of the external data and control busses.
20. The device of claim 19 , wherein said termination circuitry includes split-termination resistors.
21. The device of claim 19 , wherein said termination circuitry includes a single termination resistor coupled to a termination voltage source.
22. The device of claim 1 , wherein the internal read command identifies an internal address within the selected memory die, the controller further configured to determine at least the internal address within the selected memory die on a basis of the read command.
23. The device of claim 22 , wherein the external read command specifies a plurality of external address bits corresponding to the internal address within the selected memory die.
24. The device of claim 23 , wherein the external read command further specifies a second plurality of external address bits identifying the selected memory die.
25. The device of claim 23 , wherein the external read, command is accompanied by a signal identifying the selected memory die.
26. The device of claim 25 , wherein the signal identifying the selected memory die includes a chip enable signal.
27. The device of claim 1 , wherein the plurality of memory die are stacked.
28. The device of claim 1 , wherein each of the plurality of memory die is a dynamic random access memory (DRAM) die.
29. The device of claim 7 , the controller die further configured to provide an internal clock signal to the selected memory die along the respective internal control bus, the internal read command being synchronized with the internal clock signal.
30. The device defined in claim 29 , the selected memory die further configured to source-synchronously output the read data onto the respective internal data bus in response to receipt of the internal read command from the controller die.
31. The device defined in claim 1 , being operated in a double data rate (DDR) mode.
32. The device defined in claim 7 , the internal control bus and each respective internal data bus being operated in an un-terminated mode.
33. The device defined in claim 1 , the selected memory die further configured to asynchronously provide the read data to the controller die in response to the internal read command.
34. A multi-chip package including a plurality of semiconductor memory devices, each semiconductor memory device including:
a plurality of memory dies;
a controller die connected to an internal control bus, the controller die being configured to provide a selected one of the memory dies with an internal read command in response to an external read command, the controller die comprising a master delay locked loop (DLL) to reference an internal clock signal to a global clock signal;
wherein the selected memory die is configured to provide read data to the controller die in response to the internal read command;
wherein a first latency between sending the controller die of the internal read command and receipt by the controller die of the read data from the selected memory die differs for at least two of the memory dies, the first latency differing depending on which of the at least two dies is selected as the selected memory die;
the controller die being further configured to output the received data onto an external data bus, wherein a second latency between receipt by the controller die of the external read command and output of the read data onto the external data bus is uniform for said at least two of the memory dies when selected as the selected memory die.
35. A multi-chip package comprising a plurality of semiconductor memory devices, each semiconductor memory device including:
a plurality of memory dies;
a controller die connected to an internal control bus, the controller die being configured to provide a selected one of the memory dies with an internal read command in response to an external read command, the controller die comprising a master delay lock loop (DDL) to reference an internal clock signal to a global clock signal;
wherein the selected memory die is configured to provide read data to the controller die in response to the internal read command;
wherein a first latency between sending by the controller die of the internal read command and receipt by the controller die of the read data from the selected memory die differs for at least two of the memory dies, the first latency differing depending on which of the at least two dies is selected as the selected memory die,
the controller die further configured to output the received data onto an external data bus, wherein a second latency between receipt by the controller die of the external read command and output of the read data onto the external data bus is uniform for said at least two of the memory dies when selected as the selected memory die,
the plurality of devices mounted on a circuit board with an interface, the multi-chip package further comprising a register chip mounted on the circuit board, the register chip distributing the external control bus to each of the devices, the external data but of each of the devices being directly coupled to the interface, bypassing the register chip.