Using interrupted through-silicon-vias in integrated circuits adapted for stacking
View Patent ↗In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.
1. An integrated circuit apparatus, comprising:
a substrate;
an active circuit and interconnect layer provided on said substrate and including a plurality of constituent metal layers;
a plurality of vias extending through said substrate from said active circuit and interconnect layer to a surface of said substrate opposite said active circuit and interconnect layer;
a plurality of bond pads provided on said surface, said bond pads respectively axially aligned with and electrically connected to said vias; and
a plurality of terminals provided on said active circuit and interconnect layer, said terminals respectively axially aligned with said vias, a first subset of said terminals electrically connected to the associated vias, and a second subset of said terminals including one said terminal provided as an electrically distinct node relative to the associated axially aligned via,
wherein said one terminal is an output of circuitry in said active circuit and interconnect layer, and the associated axially aligned via is an input of said circuitry.
2. The integrated circuit apparatus of claim 1 , wherein said circuitry is a digital latching circuit.
3. The integrated circuit apparatus of claim 1 , wherein said second subset includes a plurality of said terminals provided as respective outputs of said circuitry, and wherein the respectively associated axially aligned vias are respective inputs of said circuitry.
4. The integrated circuit apparatus of claim 3 , wherein said inputs carry signals that identify said integrated circuit apparatus.
5. The integrated circuit apparatus of claim 4 , wherein said circuitry is a digital adder circuit.
6. The integrated circuit apparatus of claim 1 , wherein said second subset includes a plurality of said terminals connected through said active circuit and interconnect layer to respective ones of said vias that are axially offset from the respective terminals.
7. The integrated circuit apparatus of claim 6 , wherein said first subset includes one of said terminals connected through said active circuit and interconnect layer to one of said vias that is axially offset from said one terminal.
8. The integrated circuit apparatus of claim 7 , wherein said terminals of said second subset and said terminal of said first subset carry signals that identify said integrated circuit apparatus.
9. The integrated circuit apparatus of claim 6 , including a plurality of further vias that connect said terminals of said second subset to the associated axially offset vias.
10. The integrated circuit apparatus of claim 1 , wherein each said terminal includes a solder ball.
11. The integrated circuit apparatus of claim 10 , wherein each said terminal includes a bond pad interposed between said solder ball and said active circuit and interconnect layer.
12. The integrated circuit apparatus of claim 3 , wherein said inputs carry signals that identify said integrated circuit apparatus, and also carry signals associated with functionality of said integrated circuit apparatus.
13. An integrated circuit apparatus, comprising:
a plurality of integrated circuits according to claim 1 , the plurality of integrated circuits being arranged to form a stack of integrated circuits
wherein said terminals of one of said integrated circuits are respectively electrically connected to said bond pads of another of said integrated circuits that is adjacent said one integrated circuit in said stack.
14. The integrated circuit apparatus of claim 13 , wherein said active circuit and interconnect layers are configured to implement collectively a digital data storage apparatus.
15. The apparatus of claim 13 , wherein said one integrated circuit is identical to said another integrated circuit, and wherein said vias of said one integrated circuit are axially offset from the identically corresponding vias of said another integrated circuit.
16. The apparatus of claim 15 , wherein said one integrated circuit is interposed in said stack between said another integrated circuit and a further said integrated circuit that is also identical to said one integrated circuit and has said terminals thereof respectively connected to said bond pads of said one integrated circuit, wherein said vias of said one integrated circuit are axially offset from the identically corresponding vias of said further integrated circuit, and wherein said vias of said further integrated circuit are axially aligned with the identically corresponding vias of said another integrated circuit.
17. An electronic system, comprising:
a plurality of integrated circuits according to claim 1 , the plurality of integrated circuits being arranged to form a stack of integrated circuits
wherein said terminals of one of said integrated circuits are respectively electrically connected to said bond pads of another of said integrated circuits that is adjacent said one integrated circuit in said stack; and
electronic circuitry coupled to said bond pads of said one integrated circuit to permit signaling between said electronic circuitry and said stack of integrated circuits.
18. The system of claim 17 , wherein said active circuit and interconnect layers are configured to implement collectively a digital data storage apparatus, and wherein said electronic circuitry includes a controller for accessing said digital data storage apparatus.