High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A method of reading data in a random access memory comprising:
providing a first memory address and a read command on a first edge of a clock signal;
activating a first word line corresponding to a first segment of the first memory address;
selecting a bit line corresponding to a second segment of the first memory address;
sensing data in a memory storage element coupled to the word line and the bit line;
restoring the data in the memory storage element to a partial charge storage level;
terminating the restoring of data in the memory storage element responsive to a second edge of the clock signal; and
providing a second memory address on the second edge of the clock signal.
2. The method as claimed in claim 1 wherein restoring the data in the memory storage element comprises:
terminating the restoring of data in the memory storage element when a charge storage level of the memory storage element is about sixty percent of full level.
3. The method as claimed in claim 1 wherein restoring the data in the memory storage element comprises:
terminating the restoring of the data in the memory storage element after about one time constant of the memory storage element.
4. The method as claimed in claim 1 further comprising:
activating a second word line corresponding to a first segment of the second memory address.
5. The method as claimed in claim 1 wherein terminating the restoring of data in the memory storage element comprises deactivating the first word line.
6. The method as claimed in claim 1 , further comprising: addressing a subarray of the random access memory corresponding to a third segment of the first memory address.
7. The method as claimed in claim 1 further comprising:
activating the first word line corresponding to a first segment of the second memory address.
8. The method as claimed in claim 1 further comprising:
deactivating the word line for at least a predetermined time period; and
precharging the bit line for at least the predetermined time period.
9. The method as claimed in claim 1 further comprising outputting the data on the second edge of the clock signal.
10. The method as claimed in claim 1 further comprising outputting the data on a third edge of the clock signal.
11. The method as claimed in claim 1 wherein providing the first memory address and the read command on the first edge of the clock signal comprises:
providing the first memory address and the read command on a first rising edge of the clock signal.
12. The method as claimed in claim 1 wherein providing the second memory address on the second edge of the clock signal comprises:
providing the second memory address on a second rising edge of the clock signal.
13. The method as claimed in claim 1 wherein the method of reading data in the random access memory is a method of reading data in a dynamic random access memory.
14. The method as claimed in claim 1 wherein the method of reading data in the random access memory is a method of reading data in an embedded dynamic random access memory.