Methods for programming and reading NAND flash memory device and page buffer performing the same
View Patent ↗Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
1. A method for programming a NAND flash memory device having zero state memory cells, first state memory cells, second state memory cells and third state memory cells, each memory cell being associated with a first latch circuit and a second latch circuit, the method comprising the steps of:
(a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state;
(b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells;
(c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells; and
verifying the second state memory cells between steps (b) and (c) by applying a first verify signal to the first latch circuit and applying a second program voltage to a selected word line associated with the second state memory cells.
2. The method for programming a NAND flash memory device of claim 1 , further comprising the steps of:
verifying the first state memory cells by applying the first verify signal to the first latch circuit and applying a first program voltage to a selected word line associated with the first state memory cells; and
verifying the third state memory cells by applying a second verify signal to the first latch circuit and applying a third program voltage to a selected word line associated with the third state memory cells.
3. The method for programming a NAND flash memory device of claim 1 , wherein the MSBs of the second state memory cells, the LSBs of the first state memory cells, and the LSBs of the third state memory cells are switched from a high state to a low state.
4. The method for programming a NAND flash memory device of claim 1 , wherein a bit line power is applied to bit lines during programming the second state memory cells and during programming the first state memory cells.
5. The method for programming a NAND flash memory device of claim 4 , wherein the bit line power is adjustable between a ground voltage and a source voltage to slow down the speed of programming the first state memory cells.
6. The method for programming a NAND flash memory device of claim 1 , wherein the time of programming the first state memory cells is tuned to fit that of programming the third state memory cells.
7. The method for programming a NAND flash memory device of claim 1 , wherein each of the MSBs of the memory cells in the zero state and in the second state is latched in the corresponding second latch circuit.
8. The method for programming a NAND flash memory device of claim 7 , wherein the state of each of the MSBs of the memory cells in the zero state and in the second state is sensed by a third verify signal.
9. A method for reading a NAND flash memory device having zero state memory cells, first state memory cells, second state memory cells and third state memory cells, each memory cell being associated with a first latch circuit and a second latch circuit, the method comprising the steps of:
(a) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by applying a first verify signal and a second verify signal to the first latch circuit; and
(b) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by applying the first verify signal to the first latch circuit and by applying a third verify signal to the second latch circuit,
wherein Step (b) comprises the steps of:
reading the LSBs of the third state memory cells by applying a third read voltage to selected word lines associated with the third state memory cells;
reading the LSBs of the second state memory cells by applying a second read voltage to selected word lines associated with the second state memory cells; and
reading the LSBs of the first state memory cells and the zero state memory cells by applying a first read voltage to selected word lines associated with the first state memory cells.
10. The method for reading a NAND flash memory device of claim 9 , wherein each of the LSBs and the MSBs is outputted by a latch in the first latch circuit.
11. The method for reading a NAND flash memory device of claim 9 , further comprising a step of resetting the first latch circuit before Step (a).
12. The method for reading a NAND flash memory device of claim 9 , further comprising a step of resetting the first latch circuit and the second latch circuit between Steps (a) and (b).
13. A page buffer used in a NAND flash device having a plurality of memory cells, comprising:
a first latch circuit verifying the memory cells by a first verify signal and a second verify signal;
a second latch circuit reading the LSBs of the memory cells by a third verify signal;
a bit line voltage supply circuit providing a bit line power to a selected bit line associated with the memory cells to be programmed;
an input circuit receiving information to be programmed to the memory cells; and
a precharge circuit precharging the selected bit line.
14. The page buffer of claim 13 , further comprising a bit line selection circuit determining the selected bit line and a shielding bit line.
15. The page buffer of claim 13 , wherein the first verify signal is used to verify the MSBs of the memory cells in a second state and to verify the LSBs of the memory cells in a first state.
16. The page buffer of claim 13 , wherein the second verify signal is used to verify the LSBs of the memory cells in a third state.
17. The page buffer of claim 13 , wherein the third verify signal is used to read the LSBs of the memory cells in a second state and in a third state.
18. The page buffer of claim 13 , wherein the bit line power is adjustable from a ground voltage to a source voltage.