Power up circuit with low power sleep mode operation
View Patent ↗A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.
1. A comparator circuit for comparing a reference voltage to a node voltage in a power status indicator system, the comparator comprising:
a differential amplifier for receiving the reference voltage and node voltage and asserting an output signal only when the node voltage is greater than the reference voltage and at least one of a power up signal and a low power mode signal is asserted;
a first current source for supplying current to the differential amplifier when the low power mode signal is asserted; and
a second current source for supplying current to the differential amplifier when the power up signal is asserted.
2. The comparator circuit as claimed in claim 1 , further comprising a bias generator for supplying a bias voltage to the first and second current sources.
3. The comparator circuit as claimed in claim 2 , wherein the bias generator supplies the bias voltage to the first and second current sources when at least one of the power up signal and the low power mode signal is asserted.
4. The comparator circuit as claimed in claim 1 , wherein the first current source provides substantially zero current to the differential amplifier when the low power mode signal is de-asserted.
5. The comparator circuit as claimed in claim 1 , wherein the second current source provides substantially zero current to the differential amplifier when the power up signal is de-asserted.
6. A method of comparing a reference voltage to a node voltage in a power status indicator system, the method comprising:
supplying a first current to a differential amplifier when a low power mode signal is asserted;
supplying a second current to the differential amplifier when a power up signal is asserted; and
asserting an output signal of the differential amplifier only when the node voltage is greater than the reference voltage.
7. The method of comparing a reference voltage to a node voltage as claimed in claim 6 further comprising:
de-asserting the power up signal and thereby not supplying the first current to the differential amplifier.
8. The method of comparing a reference voltage to a node voltage as claimed in claim 7 further comprising:
de-asserting the low power mode signal and thereby not supplying the second current to the differential amplifier.