Timing vernier using a delay locked loop
View Patent ↗A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal.
1. An apparatus comprising:
first delay circuitry configured to delay an input signal by a first duration and a second duration concurrently where the first duration and the second duration are adjustable by a first control signal, to provide a pulsed signal having a duration corresponding to a difference between the first duration and the second duration;
a comparator configured to compare the duration of the pulsed signal to a reference pulse signal duration to produce a comparison output signal, in response to the comparison output signal, the first delay circuitry changing the duration of the pulsed signal to substantially correspond to the reference pulse signal duration; and
second delay circuitry configured to delay the input signal to provide a delayed input signal in response to a second control signal, the first control signal and the second control signal electrically corresponding to each other.
2. A method for producing a timing signal, comprising:
delaying an input signal by a first duration and a second duration concurrently where the first duration and the second duration are adjustable by a first control signal, to provide a pulsed signal having a duration corresponding to a difference between the first duration and the second duration;
comparing the duration of the pulsed signal to a reference pulse signal duration to produce a comparison output signal, in response to the comparison output signal, changing the duration of the pulsed signal to substantially correspond to the reference pulse signal duration; and
delaying the input signal to provide a delayed input signal in response to a second control signal, the first control signal and the second control signal electrically corresponding to each other.
3. A system for providing a delayed signal in response to an input signal, the system comprising:
a pulse provider for providing a pulsed signal in response to the input signal, the pulsed signal having an adjustable pulse duration, the adjustable pulse duration being associated with a delayed version of the input signal and being adjustable by a first control signal;
a comparator for comparing the adjustable pulse duration and a reference pulse signal duration and for adjusting the first control signal to change the adjustable pulse duration to substantially correspond to the reference pulse signal duration; and
timing circuitry for delaying the input signal to provide a the delayed input signal in response to the first control signal.
4. The method of claim 2 , wherein
the first duration corresponds to a minimum duration, the second duration corresponds to a maximum delay; and
the input signal is delayed by a first control vernier that is programmed to delay the input signal with the minimum delay, and the input signal is delayed by a second control vernier that is programmed to delay the input signal with the maximum delay.
5. The method of claim 2 , wherein the input signal delayed by the first duration corresponds to a first delayed signal and the input signal delayed by the second duration corresponds to the second delayed signal, and the pulsed signal is provided in response to active edges of the first delayed signal and the second delayed signal.
6. The method of claim 2 , wherein the input signal and the reference pulse signal are provided in response to a clock signal.
7. The method of claim 6 , further comprising
dividing the clock signal by an integer value i, the input signal being the clock signal divided by i.
8. The method of claim 6 , wherein the reference pulse signal has a duration corresponding to one clock cycle of the clock signal.
9. The method of claim 2 , further comprising
adjusting a voltage level of the first control signal in response to the reference pulse signal duration and the duration of the pulsed signal.
10. The method of claim 9 , further comprising
charging the first control signal to a supply voltage during the reference pulse signal duration; and
discharging the first control signal to a ground voltage for the duration of the pulsed signal.
11. The method of claim 2 , further comprising
filtering the first control signal to provide the second control signal.
12. The method of claim 2 , further comprising
providing a bias voltage in response to the reference pulse signal duration and the duration of the pulsed signal, the first control signal having substantially the same voltage level as the bias voltage.
13. The method of claim 12 , wherein the first control signal is provided in response to the bias voltage and a bias current, the second control signal electrically corresponding to the bias current.
14. The method of claim 13 , further comprising
converting the bias current into the second control signal, the second control signal being a voltage corresponding to the bias current.
15. The system of claim 3 , further comprising
a first control vernier for delaying the input signal by a first duration and in response to the first control signal to provide a first delayed signal, and
a second control vernier for delaying the input signal by the second duration and in response to the first control signal to provide a second delayed signal.
16. The system of claim 15 , wherein:
the first control vernier is programmable to delay the input signal with a minimum delay, and
the second control vernier is programmable to delay the input signal with a maximum delay.
17. The system of claim 15 , wherein the pulsed signal is provided in response to active edges of the first delayed signal and the second delayed signal.
18. The system of claim 15 , wherein the input signal and the reference pulse signal are provided in response to a clock signal.
19. The system of claim 18 , wherein the pulse generator is configured to divide the clock signal by an integer value i, the input signal being the clock signal divided by i.
20. The system of claim 18 , wherein the pulse generator is configured to provide the reference pulse signal having a duration corresponding to one clock cycle of the clock signal.
21. The system of claim 3 , wherein the comparator includes a charge pump for adjusting a voltage level of the first control signal in response to the reference pulse signal duration and the duration of the pulsed signal.
22. The system of claim 21 , wherein the charge pump is configured for charging the first control signal to a supply voltage during the reference pulse signal duration, and for discharging the first control signal to a ground voltage for the duration of the pulsed signal.
23. The system of claim 3 , wherein the comparator includes a charge pump for providing a bias voltage in response to the reference pulse signal duration and the duration of the pulsed signal, the first control signal having substantially the same voltage level as the bias voltage.
24. The system of claim 23 , further including a filter for filtering the first control signal to provide a second control signal and wherein the delayed signal is provided in response to the second control signal.
25. The system of claim 24 , wherein the comparator includes an analog processing circuit for providing the first control signal in response to the bias voltage and a bias current, the second control signal electrically corresponding to the bias current.
26. The system of claim 25 , wherein the timing circuitry includes a converter for converting the bias current into the second control signal, the second control signal being a voltage corresponding to the bias current.
27. The system of claim 3 , wherein the timing circuitry includes a veriner programming circuit to program a delay range of the timing circuitry.
28. The system of claim 27 , wherein the vernier programming circuit provides a programming control signal in response to a clock signal and a vernier delay code data.
29. The system of claim 28 , wherein the delayed signal provided by the timing circuitry is controlled by the first control signal and the programming control signal.
30. The system of claim 28 , wherein the vernier programming circuit includes registers and a decoder to receive the vernier delay code data and to generate the programming control signal.