Bridging device having a configurable virtual page size
View Patent ↗A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.
1. A bridge device, comprising:
a virtual page buffer for storing data;
a bridge device interface for transferring data between an external device and the virtual page buffer at a first data rate in response to a global command; and,
a memory device interface for transferring data between a memory device and the virtual page buffer at a second data rate different than the first data rate in response to a local command.
2. The bridge device of claim 1 , wherein the memory device includes a page buffer having a fixed maximum size.
3. The bridge device of claim 1 , wherein the first data rate is greater than the second data rate.
4. The bridge device of claim 1 , wherein the memory device interface is asynchronous and the bridge device interface is a synchronous interface receiving a clock signal.
5. The bridge device of claim 1 , wherein the memory device interface provides the local command in a parallel format, and the bridge device interface receives the global command in a serial format.
6. The bridge device of claim 1 , further including data path circuits for transferring data between the bridge device interface and the virtual page buffer at the first data rate.
7. The bridge device of claim 6 , wherein the data path circuits includes a data input path circuit for transferring write data received at the bridge device interface to the virtual page buffer for storage in the virtual page buffer, and a data output path circuit for transferring read data stored in the virtual page buffer to the bridge device interface.
8. The bridge device of claim 7 , wherein the virtual page buffer includes a memory having
a first input port for receiving the write data from the data input path circuit,
a first output port for providing the read data to the data output path circuit,
a second input port for receiving the read from the memory device interface, and
a second output port for providing the write data stored in the memory.
9. The bridge device of claim 8 , further including a converter circuit for receiving the write data from the second output port of the memory and generating the local command to transfer the write data to the memory device.
10. A bridge device, comprising:
a memory device interface for receiving read data at a first data rate;
a virtual page buffer for storing the read data received by the memory device interface; and,
a bridge device interface for outputting the read data stored in the memory device interface at a second data rate different than the first data rate.
11. A bridge device, comprising:
a bridge device input/output interface for receiving write data at first data rate;
a virtual page buffer for storing the write data received by the bridge device interface; and,
a memory device interface for outputting the write data stored in the virtual page buffer at a second data rate different than the first data rate.