Dynamic random access memory device and method for self-refreshing memory cells
View Patent ↗A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
1. A self-refresh controller comprising:
a timing arbitrator for providing a self-refresh request oscillation signal corresponding to an oscillation signal when enabled;
first logic circuitry operable in a first mode for enabling the timing arbitrator when a self-refresh mode of operation is entered, the first logic circuit operable in a second mode for disabling the timing arbitrator when the self-refresh mode of operation is exited;
second logic circuitry operable in the second mode for enabling the first logic circuitry to operate in the first mode when the self-refresh mode of operation is entered, the second logic circuit enabling the first logic circuit to operate in the first mode when the self-refresh mode of operation is exited.
2. The self-refresh controller of claim 1 , wherein the first logic circuitry and the second logic circuitry receive an oscillation signal.
3. The self-refresh controller of claim 2 , wherein the first mode corresponds to an inverting mode, the first logic circuitry operable in the first mode to provide a first control signal in response to a second control signal independently of the oscillation signal, the first control signal being an inverted version of the second control signal that enables the timing arbitrator.
4. The self-refresh controller of claim 3 , wherein the second mode corresponds to a latching mode for latching a first logic level of the oscillation signal in response to a mode signal at a second logic level when the self-refresh mode of operation is entered, the second logic circuitry providing the second control signal having the first logic level in response to the mode signal at the second logic level and the oscillation signal at the first logic level.
5. The self-refresh controller of claim 4 , wherein the second logic circuitry operates in the inverting mode in response to the first logic level of the mode signal when the self-refresh mode of operation is exited, the second logic circuitry inverting the first logic level of the mode signal to provide the second logic level of the second control signal.
6. The self-refresh controller of claim 5 , wherein the first logic circuitry operates in the latching mode in response to the second logic level of the second control signal, the first logic circuitry providing the first control signal having the first logic level in response to the second control signal at the second logic level and the oscillation signal at the first logic level.
7. The self-refresh controller of claim 6 , wherein the timing arbitrator is disabled by the first control signal at the first logic level.
8. The self-refresh controller of claim 3 , wherein the first logic circuitry includes an RS-type latch receiving the oscillation signal at a reset input and the second control signal at a set input.
9. The self-refresh controller of claim 4 , wherein the second logic circuitry includes an RS-type latch receiving the oscillation signal at a reset input and the mode signal at a set input.
10. A method for controlling self-refresh, comprising:
providing a self-refresh mode signal;
latching the self-refresh mode signal;
enabling logic circuitry to provide a control signal in response to a first logic level of the self-refresh mode signal and an edge of an oscillation signal;
providing a self-refresh signal corresponding to the oscillation signal when the self-refresh mode signal is latched; and,
disabling the self-refresh signal when the self-refresh mode signal is driven from the first logic level to a second logic level.
11. The method of claim 10 , wherein providing the self-refresh mode signal includes detecting a self-refresh command.
12. The method of claim 10 , wherein the logic circuitry is unresponsive to edges of the oscillation signal after the control signal is driven to the second logic level.
13. The method of claim 10 , wherein the logic circuitry is first logic circuitry and the control signal is a first control signal, and latching further includes enabling second logic circuitry to operate in an inverting mode to provide a second control signal independently of the oscillation signal in response to the first control signal.
14. The method of claim 13 , wherein the self-refresh signal is provided in response to the second control signal.
15. The method of claim 10 , wherein the logic circuitry is operated in an inverting mode in response to the second logic level of the self-refresh mode signal to drive the control signal to the first logic level.
16. The method of claim 15 , wherein the logic circuitry is first logic circuitry and the control signal is a first control signal, and second logic circuitry is operated in a latching mode in response to the first logic level of first control signal.
17. The method of claim 16 , wherein the second logic circuitry provides a second control signal having an second logic level in response to the first logic level of the first control signal and another edge of the oscillation signal.
18. The method of claim 17 , wherein the second logic circuitry is unresponsive to edges of the oscillation signal after the second control signal is driven to the second logic level.
19. The method of claim 17 , wherein disabling includes driving the self-refresh signal to the second logic level while the second control signal is at the second logic level.