Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories
View Patent ↗A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.
1. A content addressable memory having a matchline and a reference matchline, the content addressable memory comprising:
a) a current source circuit coupled to the matchline, the current source circuit applying a variable current to the matchline in response to a first control signal;
b) a first control circuit coupled to the matchline, the first control circuit sensing a voltage level of the matchline and generating the first control signal in response to the sensed voltage level and a second control signal;
c) a second control circuit coupled to the reference matchline for generating the second control signal.
2. The content addressable memory as claimed in claim 1 , wherein the reference matchline is provided with a reference current source circuit and a reference first control circuit, the reference current source circuit being substantially identical to the current source circuit and the reference first control circuit being substantially identical to the first control circuit.
3. The content addressable memory as claimed in claim 1 , wherein the second control circuit generates the second control signal in response to an output signal from the reference matchline and a matchline pre-charge signal.
4. The content addressable memory as claimed in claim 3 , wherein the second control signal includes an enable signal for enabling or disabling the current source circuit and the first control circuit.
5. The content addressable memory as claimed in claim 3 , wherein the second control circuit includes a third control circuit for modifying the output signal from the reference matchline.
6. The content addressable memory as claimed in claim 5 , wherein the third control circuit includes a delay circuit for delaying the output signal from the reference matchline.
7. The content addressable memory as claimed in claim 6 , wherein the delay circuit includes a programmable delay circuit.
8. A content addressable memory having an array of content addressable memory cells arranged in rows and columns, and a plurality of matchlines each coupled to a row of content addressable memory cells, the content addressable memory comprising a circuit for providing current to the matchline, the circuit being controlled in response to a voltage level of the matchlines such that a variable current is applied to the matchline.
9. A content addressable memory having an array of content addressable memory cells arranged in rows and columns, and a plurality of matchlines and a reference matchline each coupled to a row of content addressable memory cells, the content addressable memory comprising a circuit for providing current to the matchline and adjusting the quantity of the current being provided to the matchline, the circuit being controlled by a first control signal from the matchlines and a second control signal from the reference matchline.
10. The content addressable memory as claimed in claim 9 , wherein the first control signal includes a voltage level sensed from the matchline, and the second control signal includes a signal generated in response to an output signal from the reference matchline and a matchline pre-charge signal.
11. The content addressable memory as claimed in claim 10 , wherein the output signal is delayed through a delay circuit.