Semiconductor memory asynchronous pipeline
View Patent ↗An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.
1. A synchronous DRAM device comprising;
a memory having addressable memory elements;
a plurality of read amplifiers for sensing N bits of read data from the memory;
a plurality of latches for receiving data from the read amplifiers, said latches organized in M groups of N latches each, each group latching the data from the read amplifiers at one time;
a counter for enabling a single group of latches at one time;
a delay locked loop for providing an output clock signal synchronized to a system clock input signal; and
a plurality of data output buffers for latching outputs of the plurality of latches on edges of the output clock signal and providing output data synchronized with edges of the system clock input signal.
2. The synchronous DRAM device of claim 1 where N=32.
3. The synchronous DRAM device of claim 1 where M=3.
4. The synchronous DRAM device of claim 1 wherein the plurality of output buffers provide output data synchronized with rising and falling edges of the system clock input signal.
5. The synchronous DRAM device of claim 4 wherein each of the M groups of N latches is comprised of a group of N/2 latches receiving data to be output in synchronization with rising edges of the system clock input signal and a group of N/2latches receiving data to be output in synchronization with falling edges of the system clock input signal.
6. The synchronous DRAM device of claim 5 where M=6.
7. The synchronous DRAM device of claim 1 wherein the counter is a binary counter.
8. The synchronous DRAM device of claim 7 wherein outputs of the binary counter are decoded to provide enable signals for the plurality of latches.
9. The synchronous DRAM device of claim 1 wherein the output clock signal leads the system clock signal.
10. The synchronous DRAM device of claim 1 wherein each group of latches receives data to be output by the output buffers in synchronization with a plurality of edges of the system clock input signal.
11. The synchronous DRAM device of claim 10 wherein each group of latches receives data to be output by the output buffers in synchronization with two edges of the system clock input signal.
12. The synchronous DRAM device of claim 11 wherein each group of latches receives data to be output by the output buffers in synchronization with a rising edge and a falling edge of the system clock input signal.
13. A method of providing a data output, comprising:
sensing, via a plurality of read amplifiers, N bits of read data from a memory having addressable memory elements;
receiving the data to a plurality of latches, said latches organized in M groups of N latches each, each group latching the data from the read amplifiers at one time;
enabling, via a counter, a single group of latches at one time;
providing an output clock signal synchronized to a system clock input signal;
latching outputs of the plurality of latches on edges of the output clock signal; and
providing output data synchronized with edges of the system clock input signal.
14. The method of claim 13 where N=32.
15. The method of claim 13 where M=3.
16. The method of claim 13 wherein the output data is synchronized with rising and falling edges of the system clock input signal.
17. The method of claim 16 wherein each of the M groups of N latches is comprised of a group of N/2 latches receiving data to be output in synchronization with rising edges of the system clock input signal and a group of N/2 latches receiving data to be output in synchronization with falling edges of the system clock input signal.
18. The method of claim 17 where M=6.
19. The method of claim 13 wherein the counter is a binary counter.
20. The method of claim 19 further comprising decoding outputs of the binary counter to provide enable signals for the plurality of latches.
21. The method of claim 13 wherein the output clock signal leads the system clock signal.
22. The method of claim 13 further comprising receiving, at each group of latches, data to be output in synchronization with a plurality of edges of the system clock input signal.
23. The method of claim 22 wherein each group of latches receives data to be output in synchronization with two edges of the system clock input signal.
24. The method of claim 23 wherein each group of latches receives data to be output in synchronization with a rising edge and a falling edge of the system clock input signal.