High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A system comprising:
a memory device for performing read, write, and refresh operations, said memory device comprising:
a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line;
a word line enable device for asserting a selected one of said word lines;
a column select device for asserting a selected one of said bit line pairs; and
a timing circuit for controlling said word line enable device, said column select device, and said read, write, and refresh operations in response to a word line timing pulse, wherein said read, write, and refresh operations are performed in the same amount of time.
2. A system comprising:
a memory device for storing data in address locations specified by input addresses, said memory device responsive only to read, write and refresh commands, each of said commands having a uniform latency independent of said input addresses.
3. A system as claimed in claim 2 wherein said memory device comprises a dynamic random access memory (DRAM).
4. A system as claimed in claim 2 wherein said memory device comprises an embedded dynamic random access memory (DRAM) macrocell.
5. A system as claimed in claim 2 wherein independent of input address said read command includes a full row access operation comprising the steps of:
bit line pre-charge and equalization;
word line address decoding and word line assertion;
memory cell access to an associated bit line pair;
bit line sensing;
memory cell restoration; and
word line de-assertion.
6. A system as claimed in claim 2 wherein said memory device is capable of receiving a new command on every leading edge of a system clock.
7. A system as claimed in claim 2 wherein said memory device is capable of performing a read and write operation in a single system clock cycle in response to a simultaneous read/write command.
8. A system as claimed in claim 7 wherein said simultaneous read/write operation comprises performing a write operation during a first portion of row cycle while bit line sense amplifiers are amplifying differential voltage on selected bit lines and before full differential voltage levels are established on said bit lines.
9. A system as claimed in claim 5 wherein said steps of word line address decoding and bit line precharge and equalizing are performed substantially simultaneously during a first portion of a row cycle.
10. A system as claimed in claim 2 wherein said memory device comprises a synchronous interface that accepts and performs commands a rate of one command per period of an interface input clock.
11. A system as claimed in claim 10 wherein the synchronous interface comprises a read data latency of one or more periods of the interface input clock.
12. A system as claimed in claim 2 wherein said memory device comprises an asynchronous interface that accepts and performs commands a rate of one command per active edge of an interface input strobe.
13. A system as claimed in claim 2 wherein said memory device comprises a synchronous interface that accepts and performs commands a rate of one command per two or more periods of an interface input clock.
14. A system as claimed in claim 2 wherein said memory device comprises a synchronous interface that accepts and performs commands a rate of one command per two periods of an interface input clock.
15. A memory device for performing read, write, and refresh operations, said memory device comprising:
a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line;
a word line enable device for asserting a selected one of said word lines;
a column select device for asserting a selected one of said bit line pairs;
a timing circuit for controlling said word line enable device, said column select device, and said read, write, and refresh operations in response to a word line timing pulse, wherein said read, write, and refresh operations are performed in the same amount of time; and
one or more surplus sub-arrays for repairing defective sub-arrays.
16. A system as claimed in claim 1 wherein a type of the memory device is selected from a list consisting of Static Random Access Memory (SRAM), Electrically Programmable Read Only Memory (EPROM), Flash EPROM, and Ferroelectric Random-Access Memory (FRAM).
17. A system as claimed in claim 2 wherein a type of the memory device is selected from a list consisting of Static Random Access Memory (SRAM), Electrically Programmable Read Only Memory (EPROM), Flash EPROM, and Ferroelectric Random-Access Memory (FRAM).
18. A memory device as claimed in claim 15 wherein a type of the memory device is selected from a list consisting of Static Random Access Memory (SRAM), Electrically Programmable Read Only Memory (EPROM), Flash EPROM, and Ferroelectric Random-Access Memory (FRAM).