Double data rate output circuit and method
View Patent ↗A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
1. A double data rate output circuit comprising:
an edge detector for receiving a first clock signal and providing a second clock signal having twice a frequency of the first clock signal to an edge detector output;
a multiplexer for receiving rising edge data having a data rate corresponding to the frequency of the first clock signal at a first input, receiving falling edge data having a data rate corresponding to the frequency of the first clock signal at a second input, and, based on a selection signal received at a selection input, alternately providing the data received at the first input and the second input to a multiplexer output;
an edge triggered flip-flop having a data input coupled to the multiplexer output, a clock input coupled to the edge detector output, and a flip-flop output providing data received at the data input and latched on edges of the clock received at the clock input; and
a data output buffer having an input coupled to the flip-flop output and an output coupled to a data output terminal,
wherein the double data rate output circuit provides rising edge data and falling edge data on the data output terminal at a data rate corresponding to twice the frequency of the first clock signal.
2. The double data rate output circuit as claimed in claim 1 wherein the edge detector comprises a rising edge detector and a falling edge detector.
3. The double data rate output circuit as claimed in claim 2 wherein the rising edge detector and the falling edge detector each comprise a two input logic gate and an inverting delay circuit.
4. The double data rate output circuit as claimed in claim 2 wherein the edge detector output is coupled to the output of a logic gate having inputs coupled to the rising edge detector and the falling edge detector.
5. The double data rate output circuit as claimed in claim 1 wherein the first clock signal is provided by a Delay-Locked Loop (DLL).
6. The double data rate output circuit as claimed in claim 1 wherein the first clock signal is a differential clock signal comprising a true and a complement first clock signals.
7. The double data rate output circuit as claimed in claim 6 wherein the edge detector comprises a rising edge detector having an input coupled to the true first clock signal and a falling edge detector having an input coupled to the complement first clock signal.
8. The double data rate output circuit as claimed in claim 1 wherein the selection signal is a clock signal having a frequency substantially equal to the frequency of the first clock signal.
9. The double data rate output circuit as claimed in claim 8 wherein the selection signal is provided by a flip-flop clocked by the edge detector.
10. The double data rate output circuit as claimed in claim 9 wherein the flip-flop clocked by the edge detector is a set-reset flip-flop.
11. The double data rate output circuit as claimed in claim 9 wherein the output of the flip-flop is delayed to provide the selection signal.
12. The double data rate output circuit as claimed in claim 2 wherein the selection signal is provided by a set-reset flip-flop having a set input coupled to a selected one of the rising edge detector and the falling edge detector and a reset input coupled to one of the rising edge detector and the falling edge detector other than the selected one of the rising edge detector and the falling edge detector.
13. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by latches.
14. The double data rate output circuit as claimed in claim 13 wherein a selected one of the rising edge data and the falling edge data is latched in an edge triggered flip-flop clocked by the first clock signal and provided to the multiplexer.
15. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by a Static Random Access Memory (SRAM).
16. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by a dual-port Static Random Access Memory (SRAM).
17. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by a Content Addressable Memory (CAM).
18. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by a Dynamic Random Access Memory (DRAM).
19. The double data rate output circuit as claimed in claim 1 wherein the rising edge data and the falling edge data are provided by registers in a logic block.
20. A method for providing a double data rate output signal, the method comprising:
receiving a first clock signal;
receiving a selection signal having a frequency substantially equal to a frequency of the first clock signal;
receiving rising edge data and falling edge data each having a data rate corresponding to the frequency of the first clock signal;
detecting edges of the first clock signal to provide a second clock signal having a frequency twice the frequency of the first clock signal;
alternately selecting the rising edge data and the falling edge data based on the selection signal to provide a double data rate data signal; and
synchronizing the double data rate data signal with the second clock signal to provide the double data rate output signal.
21. The method for providing a double data rate output signal as claimed in claim 20 wherein detecting edges of the first clock signal comprises detecting rising and falling edges of the first clock signal.
22. The method for providing a double data rate output signal as claimed in claim 21 wherein detecting rising and falling edges of the first clock signal comprises delaying the first clock signal.
23. The method for providing a double data rate output signal as claimed in claim 21 wherein providing the second clock signal comprises combining the detection of rising and falling edges of the first clock signal.
24. The method for providing a double data rate output signal as claimed in claim 20 further comprising providing the first clock signal with a Delay-Locked Loop (DLL).
25. The method for providing a double data rate output signal as claimed in claim 20 wherein receiving the first clock signal comprises receiving a true and a complement first clock signals.
26. The method for providing a double data rate output signal as claimed in claim 20 further comprising clocking a flip-flop with the second clock signal to provide the selection signal.
27. The method for providing a double data rate output signal as claimed in claim 20 further comprising clocking a set-reset flip-flop with the second clock signal to provide the selection signal.
28. The method for providing a double data rate output signal as claimed in claim 26 further comprising delaying the output of the flip-flop to provide the selection signal.
29. The method for providing a double data rate output signal as claimed in claim 20 further comprising latching the output of a data storage circuit to provide the rising edge data and the falling edge data.
30. The method for providing a double data rate output signal as claimed in claim 29 further comprising additionally latching a portion of the output of the data storage circuit to provide a selected one of the rising edge data and the falling edge data.