Antifuse structure and method of use
View Patent ↗An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.
1. An electronic device comprising:
a substrate; and
an antifuse disposed on the substrate, the antifuse including:
a body;
a conductive terminal;
an ohmic contact in the body, the ohmic contact accessible to an external pin, the ohmic contact having a conductivity type different from that of the conductive terminal;
an insulator between the body and the conductive terminal.
2. The electronic device of claim 1 , wherein the substrate is of a first conductivity type and the body includes a well of a second conductivity type.
3. The electronic device of claim 1 , wherein the substrate is of a first conductivity type and the conductive terminal is of the first conductivity type.
4. The electronic device of claim 1 , wherein the electronic device is configured in an integrated circuit.
5. The electronic device of claim 1 , wherein the electronic device is configured as a memory.
6. The electronic device of claim 1 , wherein the electronic device is configured in a system.
7. An electronic device comprising:
a substrate; and
an antifuse disposed on the substrate, the antifuse including:
a body isolated by an isolation insulator;
an ohmic contact in the body, the ohmic contact accessible to an external pin;
a conductive terminal, the conductive terminal having a conductivity type different from that of the ohmic contact; and
a gate insulator between the body and the conductive terminal.
8. The electronic device of claim 7 , wherein the body comprises silicon isolated by the isolation insulator.
9. The electronic device of claim 8 , wherein:
the body comprises n-type silicon;
the ohmic contact comprises an n+-type diffusion region in the body;
the isolation insulator comprises a shallow trench isolation insulator comprising oxide and further comprises a layer of silicon-on-insulator oxide between the body and a silicon substrate;
the gate insulator comprises a layer of oxide; and
the conductive terminal comprises a layer of n+-type polysilicon.
10. The electronic device of claim 8 , wherein:
the body comprises p-type silicon;
the ohmic contact comprises a p+-type diffusion region in the body;
the isolation insulator comprises a shallow trench isolation insulator comprising oxide and further comprises a layer of silicon-on-insulator oxide between the body and a silicon substrate;
the gate insulator comprises a layer of oxide; and
the conductive terminal comprises a layer of p+-type polysilicon.
11. The electronic device of claim 8 , wherein:
the body comprises n-type silicon;
the ohmic contact comprises an n+-type diffusion region in the body;
the isolation insulator comprises a shallow trench isolation insulator comprising oxide and further comprises a layer of silicon-on-insulator oxide between the body and a silicon substrate;
the gate insulator comprises a layer of oxide; and
the conductive terminal comprises a layer of p+-type polysilicon.
12. The electronic device of claim 8 , wherein:
the body comprises p-type silicon;
the ohmic contact comprises a p+-type diffusion region in the body;
the isolation insulator comprises a shallow trench isolation insulator comprising oxide and further comprises a layer of silicon-on-insulator oxide between the body and a silicon substrate;
the gate insulator comprises a layer of oxide; and
the conductive terminal comprises a layer of n+-type polysilicon.
13. An integrated circuit comprising:
a circuit;
a plurality of antifuses, each antifuse including:
a first conductive terminal of a first conductivity type coupled to the circuit to receive a first programming voltage; and
a well of a second conductivity type in a substrate of the first conductivity type;
an insulator between the well and the first conductive terminal; and
a ohmic contact in the well; and
an external pin in the integrated circuit coupled to the ohmic contact of each antifuse to receive a second programming voltage.
14. The integrated circuit of claim 13 , wherein:
the circuit comprises a programming logic circuit;
the substrate comprises a p-type silicon substrate;
the well comprises an n-type well in the substrate;
the ohmic contact comprises an n+-type diffusion region;
the insulator comprises a layer of oxide; and
the first conductive terminal comprises a layer of p-type polysilicon.
15. The integrated circuit of claim 13 , wherein:
the circuit comprises a programming logic circuit;
the substrate comprises an n-type silicon substrate;
the well comprises a p-type well in the substrate;
the ohmic contact comprises a p+-type diffusion region;
the insulator comprises a layer of oxide; and
the first conductive terminal comprises a layer of n-type polysilicon.
16. A memory comprising:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a body;
a conductive terminal;
an ohmic contact in the body, the ohmic contact accessible to an external pin, the ohmic contact having a conductivity type different from that of the conductive terminal; and
an insulator between the body and the conductive terminal.
17. The memory of claim 16 , wherein the substrate is of a first conductivity type and the body includes a well of a second conductivity type.
18. The memory of claim 16 , wherein the substrate is of a first conductivity type and the conductive terminal is of the first conductivity type.
19. The memory of claim 16 , wherein the array is disposed on the substrate.
20. The memory of claim 16 , wherein the antifuses are located in an address decoder in the memory.
21. The memory of claim 16 , wherein the memory is a static random access memory.
22. A memory comprising:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a first conductive terminal of a first conductivity type coupled to a read circuit to receive a first programming voltage; and
a well of a second conductivity type in a substrate of the first conductivity type;
an insulator between the well and the first conductive terminal; and
a ohmic contact in the well; and
an external pin in the memory coupled to the ohmic contact of each antifuse to receive a second programming voltage.
23. The memory of claim 22 , wherein the read circuit includes a power-up circuit to provide a power-up voltage to the first conductive terminal.
24. The memory of claim 22 , wherein the read circuit includes a resistor coupling the first conductive terminal to a supply voltage.
25. The memory of claim 22 , wherein the substrate includes a p-type silicon substrate, the well includes an n-type well in the substrate, the ohmic contact includes an n+-type diffusion region, and the first conductive terminal includes a layer of p-type polysilicon.
26. The memory of claim 22 , wherein the substrate includes an n-type silicon substrate, the well includes a p-type well in the substrate, the ohmic contact includes a p+-type diffusion region, and the first conductive terminal includes a layer of n-type polysilicon.
27. The memory of claim 22 , wherein the memory is a static random access memory.
28. A memory comprising:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a body isolated by an isolation insulator;
an ohmic contact in the body accessible to an external pin;
a conductive terminal; and
a gate insulator between the body and the conductive terminal.
29. The memory of claim 28 , wherein the substrate includes a layer of silicon-on-insulator oxide between the body and a silicon substrate.
30. The memory of claim 29 , wherein the isolation insulator is configured as a shallow trench isolation insulator having an oxide.
31. The memory of claim 30 , wherein the body includes n-type silicon, the ohmic contact includes an n+-type diffusion region in the body, and the conductive terminal includes a layer of n+-type polysilicon.
32. The memory of claim 30 , wherein the body includes p-type silicon, the ohmic contact includes a p+-type diffusion region in the body, and the conductive terminal includes a layer of p-type polysilicon.
33. The memory of claim 30 , wherein the body includes n-type silicon, the ohmic contact includes an n+-type diffusion region in the body, and the conductive terminal includes a layer of p+-type polysilicon.
34. The memory of claim 30 , wherein the body includes p-type silicon, the ohmic contact includes a p+-type diffusion region in the body, and the conductive terminal includes a layer of n+-type polysilicon.
35. The memory of claim 28 , wherein the conductive terminal is coupled to a read circuit of the memory.
36. The memory of claim 28 , wherein the antifuses are located in an address decoder in the memory.
37. A system comprising:
a processor;
a memory coupled to the processor, the memory including:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a body;
a conductive terminal;
an ohmic contact in the body, the ohmic contact accessible to an external pin, the ohmic contact having a conductivity type different from that of the conductive terminal; and
an insulator between the body and the conductive terminal.
38. The system of claim 37 , wherein the memory includes a read circuit having a power-up circuit to provide a power-up voltage to the first conductive terminal.
39. A system comprising:
a processor;
a memory coupled to the processor, the memory including:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a body;
a conductive terminal;
an ohmic contact in the body, the ohmic contact accessible to an external pin; and
an insulator between the body and the conductive terminal, wherein the memory includes a read circuit having a resistor coupling the conductive terminal to a supply voltage.
40. The system of claim 37 , wherein the substrate includes a layer of silicon-on-insulator oxide between the body and a silicon substrate.
41. A system comprising:
a processor;
a memory coupled to the processor, the memory including:
an array of memory cells; and
a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array; each antifuse including:
a body;
a conductive terminal;
an ohmic contact in the body, the ohmic contact accessible to an external pin; and
an insulator between the body and the conductive terminal, wherein the body is isolated by a shallow trench isolation insulator having an oxide.
42. The system of claim 37 , wherein the system is an information handling system.
43. The system of claim 37 , wherein the information handling system includes a computer.
44. A memory device comprising:
an array of memory cells;
an address decoder;
a plurality of input/output paths;
an input/output control circuit; and
an antifuse bank comprising:
a programming logic circuit;
an external pin; and
a plurality of antifuses disposed on a substrate, each antifuse comprising:
a well of a first conductivity type in the substrate of a second conductivity type, the well being coupled to the external pin by an ohmic contact in the well;
a first conductive terminal of the second conductivity type coupled to the programming logic circuit; and
an insulator between the well and the first conductive terminal.
45. The memory device of claim 44 , wherein:
the substrate comprises a p-type silicon substrate;
the well comprises an n-type well in the substrate;
the ohmic contact comprises an n+-type diffusion region;
the insulator comprises a layer of oxide; and
the first conductive terminal comprises a layer of p-type polysilicon.
46. The memory device of claim 44 , wherein:
the substrate comprises an n-type silicon substrate;
the well comprises a p-type well in the substrate;
the ohmic contact comprises a p+-type diffusion region;
the insulator comprises a layer of oxide; and
the first conductive terminal comprises a layer of n-type polysilicon.
47. The electronic device of claim 1 , wherein the ohmic contact has two portions separated by the body, the two portions in electrical contact.
48. The electronic device of claim 13 , wherein the ohmic contact has two portions separated by the body, the two portions in electrical contact.
49. The electronic device of claim 16 , wherein the ohmic contact has two portions separated by the body, the two portions in electrical contact.
50. The electronic device of claim 44 , wherein the ohmic contact has two portions separated by the body, the two portions in electrical contact.