Patent Assignment
Reel/Frame 024225/0878
Corrective Assignment to Correct the to Correct the Assignees' Address Previously Recorded on Reel 023220 Frame 0243. Assignor(S) Hereby Confirms the Mosaid Technologies Incorporated 6 Sauble Drive, Suite 203, Ottawa,Ontario, Canada K2K 2X1.
Recorded: 2010-04-14
Received: 2010-04-14
Pages: 37
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2009-06-09
Assignee
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD, SUITE 203, OTTAWA, CAX, K2K 2X1, CANADA
Covered Properties
(30)
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Application:
11/298,978 →
Capacitor Structure
Application:
10/932,503 →
Antifuse Structure and Method of Use
Application:
10/931,714 →
Integrated Circuits with Rhodium-Rich Structures
Application:
10/850,664 →
Solvent Prewet and Method to Dispense the Solvent Prewet
Application:
10/836,053 →
System for Testing Integrated Circuit Devices
Application:
10/835,945 →
Polyester-Polyether Hybrid Urethane Acrylate Oligomer for Uv Curing Pressure Sensitive Adhesives
Application:
10/832,871 →
Chemical Vapor Deposition of Titanium from Titanium Tetrachloride and Hydrocarbon Reactants
Application:
10/706,244 →
A Vertical Transistor Structure Having a Gate Region Formed on a Drain Region and a Source Region Overlying the Uppermost Layer of the Gate Region.
Application:
10/379,494 →
Device Addressing Gas Contamination in a Wet Process
Application:
10/346,980 →
System for Testing Integrated Circuit Devices
Application:
10/295,499 →
Polishing Systems, Methods of Polishing Substrates, and Methods of Cleaning Polishing Slurry from Substrate Surfaces
Application:
10/271,522 →
Capacitor Structure
Application:
10/145,250 →
Capacitor Structure
Application:
10/145,435 →
Circuit and Method for Testing a Memory Device
Application:
10/099,220 →
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Application:
10/051,768 →
Selective Method to Form Roughened Silicon
Application:
10/039,022 →
Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
Application:
10/046,497 →
Boride Electrodes and Barriers for Cell Dielectrics
Application:
09/941,759 →
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Application:
09/942,157 →
Solvent Prewet and Method and Apparatus to Dispense the Solvent Prewet
Application:
09/941,476 →
Dilute Cleaning Composition and Method for Using Same
Application:
09/935,234 →
Collimated Sputter Deposition Monitor Using Sheet Resistance
Application:
09/932,233 →
Dilute Cleaning Composition and Method for Using Same
Application:
09/929,640 →
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Application:
09/887,612 →
Method of Forming a Capacitor and a Capacitor Construction
Application:
09/876,102 →
Method of Anti-Fuse Repair
Application:
09/845,794 →
Semiconductor Circuit Design Methods, Semiconductor Processing Methods and Integrated Circuitry
Application:
09/823,104 →
Sequential Pulse Deposition
Application:
09/782,207 →
Method of Forming a Capacitor
Application:
09/779,219 →