Dual function compatible non-volatile memory device
View Patent ↗A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
1. A method for setting an operating mode of a memory device, the method comprising:
powering up the memory device and detecting a power supply voltage reaching a predetermined level;
detecting a voltage of a port when the power supply voltage reaches the predetermined level,
responding to the voltage of the port to provide a response after the memory device has completed power up; and
setting an operation mode of circuitry of the memory device in response to the response.
2. The method of claim 1 , wherein the step of setting comprises:
selecting signals corresponding to the operating mode based on the response for use by the circuitry of the memory device.
3. The method of claim 2 , wherein the voltage is a first voltage and the step of selecting comprises:
detecting a second voltage different from the first voltage to provide a voltage response as the response, the voltage response corresponding to a complement of the response in a case where the absence of the voltage is undetected.
4. The method of claim 3 , wherein the step of setting further comprises:
setting the operation mode of the circuitry in another operating mode in response to the complement of the response.
5. The method of claim 4 , wherein the memory device has at least one other port, and the step of setting further comprises:
receiving a signal containing information at the at least one other port; and
configuring the at least one other port to receive the information contained in the signal in response to one of the response and the complement of the response, the circuitry operating in response to the information.
6. The method of claim 5 , wherein the step of receiving comprises:
receiving the signal containing information corresponding to at least one of control information and data information at the at least on other port.
7. The method of claim 1 , wherein the voltage is the power supply voltage.
8. The method of claim 1 , wherein the port includes an existing port used in the first operating mode, the existing port being unused in the second operating mode.
9. The method of claim 8 , wherein a low logic level of the existing port is latched when the power supply voltage has reached the predetermined level.
10. The method of claim 9 , wherein the existing port can be switched between high and low logic levels after the low logic level is latched.
11. The method of claim 1 , wherein the port is unused in the first operating mode and the second operating mode.
12. The method of claim 1 , wherein setting includes driving a mode signal to a first logic level when the voltage is detected on the port, the mode signal being driven to a second logic level when the voltage is undetected on the port.
13. The method of claim 12 , wherein setting includes coupling control and data ports of the memory device to asynchronous circuits in response to the first logic level of the mode signal, and coupling the control and data ports of the memory device to synchronous circuits in response to the second logic level of the mode signal.
14. The method of claim 13 , wherein setting further includes disconnecting the power supply voltage from the synchronous circuits in response to the first logic level of the mode signal, and disconnecting the power supply voltage from the asynchronous circuits in response to the second logic level of the mode signal.
15. The method of claim 13 , wherein the asynchronous circuits includes an asynchronous command decoder for providing decoded asynchronous command signals, and a synchronous command decoder for providing decoded synchronous command signals.
16. The method of claim 15 , wherein setting further includes selectively passing one of the decoded asynchronous command signals and the decoded synchronous command signals to control logic in response to the mode signal.
17. The method of claim 16 , wherein the decoded asynchronous command signals and the decoded synchronous command signals are identical to each other.