Memory with output control
View Patent ↗An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
1. A device into which a clock input (CLKI) signal is received, and out of which a clock output (CLKO) signal is transmitted, the device comprising:
flash memory;
input connections for receiving data, an output enable signal, and the CLKI signal that provides for synchronization with respect to the received data;
output connections for transmitting the CLKO signal, and for transmitting the data in response to the output enable signal being held to a logic level for a number of edges of the CLKO signal that provides for other synchronization; and
a Phase Lock Loop (PLL) to match any phase difference between the CLKI and CLKO signals.
2. The device as claimed in claim 1 wherein the other synchronization is synchronization with respect to the transmitted data.
3. The device as claimed in claim 1 wherein the CLKI signal is a Serial Clock Input (SCLKI) signal.
4. The device as claimed in claim 1 wherein the CLKO signal is a Serial Clock Output (SCLKO) signal.
5. The device as claimed in claim 1 further comprising circuits for capturing and storing the data in the flash memory.
6. The device as claimed in claim 1 wherein the input and output connections for receiving and transmitting data comprise data ports.
7. The device as claimed in claim 1 wherein the edges are one of rising edges, falling edges and both rising and falling edges of the CLKO signal.
8. The memory device as claimed in claim 1 , wherein a first bit of the data is transmitted by the output connections after a first delay from the output enable signal being driven to the active state, and a last bit of the data is provided at a second delay after the output enable signal is driven to an inactive state.
9. A device into which a clock input (CLKI) signal is received, and out of which a clock output (CLKO) signal is transmitted, the device comprising:
flash memory;
input connections for receiving data, an output enable signal, and the CLKI signal that provides for synchronization with respect to the received data;
output connections for transmitting the CLKO signal, and for transmitting the data in response to an output enable signal being held to a logic level for a number of edges of the CLKO signal that provides for other synchronization; and
a DLL to match any phase difference between the CLKI and CLKO signals.
10. The device as claimed in claim 9 wherein the other synchronization is synchronization with respect to the transmitted data.
11. The device as claimed in claim 9 wherein the CLKI signal is a Serial Clock Input (SCLKI) signal.
12. The device as claimed in claim 9 wherein the CLKO signal is a Serial Clock Output (SCLKO) signal.
13. The device as claimed in claim 9 further comprising circuits for capturing and storing the data in the flash memory.
14. The device as claimed in claim 9 wherein the input and output connections for receiving and transmitting data comprise data ports.
15. The device as claimed in claim 9 wherein the number of edges are one of rising edges, falling edges and both rising and falling edges of the CLKO signal.
16. The memory device as claimed in claim 9 , wherein a first bit of the data is transmitted by the output connections after a first delay from the output enable signal being driven to the active state, and a last bit of the data is provided at a second delay after the output enable signal is driven to an inactive state.
17. A flash memory system having a plurality of serially connected flash memory devices comprising:
a first flash memory device having a plurality of data input ports for receiving data from an external source, a plurality of data output ports for providing data received at the data input ports, a plurality of control input ports for receiving at least an output enable signal from the external source, and a plurality of control output ports for providing at least the output enable signal, and the first flash memory device being configured to provide the data in response to the output enable signal; and
a second flash memory device having a plurality of data input ports for receiving the data provided from the data output ports of the first flash memory device, a plurality of data output ports for providing the data received at the data input ports, a plurality of control input ports for receiving at least the output enable signal, and a plurality of control output ports for providing at least the output enable signal, and the second flash memory device being configured to provide the data in response to the output enable signal.
18. The flash memory system of claim 17 wherein the plurality of control output ports of the first flash memory device provide echoing values received at the control input ports of the first flash memory device to the second flash memory device.
19. The flash memory system of claim 17 wherein the external source is a memory controller.
20. The flash memory system of claim 17 wherein each of the plurality of serially connected flash memory devices further comprise a plurality of flash memory blocks and a plurality of serial data link interfaces.
21. The flash memory system of claim 20 wherein the plurality of flash memory blocks comprise a plurality of flash memory banks.
22. A device into which a clock input (CLKI) signal is received, the device comprising:
flash memory;
at least one port for receiving a command, the CLKI signal providing synchronization with respect to the command;
control signal ports for receiving two control signals, the command being latched on edges of the CLKI signal while only one of the two control signals is held at a logic level for at least a duration of time the command is provided to the device; and,
core circuitry for executing an operation corresponding to the command.
23. The device of claim 22 , wherein the duration of time corresponds to a number of edges of the CLKI signal.
24. The device of claim 23 , wherein the number of edges corresponds to one of rising edges, falling edges and both rising and falling edges of the CLKI signal.
25. The device of claim 22 , wherein the only one of the two control signals is held at the logic level while the command is provided to the device.
26. The device of claim 25 , wherein the only one of the two control signals transitions from an inactive logic level to an active logic level synchronously with an edge of the CLKI signal, and transitions from the active logic level to the inactive logic level synchronously with another edge of the CLKI signal.
27. The device of claim 22 , wherein the at least one port includes a data port that latches data on edges of the CLKI signal while the only one of the two control signals is held at a logic level for a duration of time the data is provided to the device.
28. The device of claim 22 , wherein the one of the two control signals is an input enable signal, and the other of the two control signals is an output enable signal.
29. The device of claim 28 , wherein the device further includes
read circuitry configured to obtain read data from said flash memory to facilitate subsequent transmission of the read data; and,
an output buffer configured to receive the read data and to transmit the read data through an output port in response to the output enable signal, the output enable signal being held at another logic level for a period of time that delineates a length of said read data transmitted from said output port.