Semiconductor devices having a pocket line and methods of fabricating the same
View Patent ↗In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket line extends across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate. The pocket line includes a pocket conductive layer line, a lower metal layer line, and an upper metal layer line, which are sequentially stacked on the pocket insulating layer pattern. The device further may further include a line capping layer pattern placed on the pocket line. The line capping layer pattern and the pocket conductive layer line may surround the lower and upper metal layer lines.
1. A method of fabricating a semiconductor device, the method comprising:
forming an active region isolated by a device isolation layer formed in a semiconductor substrate;
forming a molding hole in the semiconductor substrate on the active region;
forming self-alignment masks on the semiconductor substrate having the molding hole to traverse the active region, the self-alignment masks exposing the molding hole;
forming a pocket insulating layer on the semiconductor substrate having the self-alignment masks;
sequentially forming a pocket conductive layer, and lower and upper metal layers on the pocket insulating layer;
performing an etch process on the upper metal layer, the lower metal layer, and the pocket conductive layer, using the self-alignment masks as etch masks, to form a pocket pattern including a pocket conductive layer pattern, a lower metal layer pattern and an upper metal layer pattern;
forming a line capping layer pattern on the pocket pattern; and
patterning the pocket pattern, and the pocket insulating layer, using the line capping layer pattern as an etch mask, to form a pocket insulating layer pattern and a pocket line including a pocket conductive layer line, a lower metal layer line and an upper metal layer line.
2. The fabrication method according to claim 1 , wherein the forming self-alignment masks comprises:
forming an undoped polysilicon layer on the semiconductor substrate having the molding hole;
forming a photoresist layer on the undoped polysilicon layer;
performing a photolithographic process on the photoresist layer to form a photoresist pattern exposing the undoped polysilicon layer; and
performing an etch process on the undoped polysilicon layer by using the photoresist pattern as an etch mask.
3. The fabrication method according to claim 1 , wherein the self-alignment masks are formed of a doped polysilicon layer.
4. The fabrication method according to claim 1 , wherein the pocket conductive layer is formed of a conductive layer having the same etching selectivity ratio as the self-alignment masks.
5. The fabrication method according to claim 1 , wherein the pocket conductive layer is formed of a conductive layer having an etching selectivity ratio different from the self-alignment masks.
6. The fabrication method according to claim 1 , wherein the lower and upper metal layers are formed of tungsten nitride (WN) and tungsten (W), respectively.
7. The fabrication method according to claim 1 , wherein the line capping layer is formed of an insulating layer having an etching selectivity ratio different from the pocket conductive layer.
8. The fabrication method according to claim 1 , wherein the performing the etch process comprises chemical and mechanical polishing.
9. The fabrication method according to claim 1 , wherein the performing the etch process comprises etching back.
10. The fabrication method according to claim 1 , wherein the forming the line capping layer pattern comprises:
forming a line capping layer on the semiconductor substrate having the pocket pattern;
forming a photoresist layer on the line capping layer;
performing a photolithographic process on the photoresist layer to form a photoresist pattern; and
performing an etch process on the line capping layer using the photoresist pattern as an etch mask.
11. The fabrication method according to claim 1 , wherein the line capping layer pattern and the pocket conductive layer line surround the lower and upper metal layer lines.
12. A method for forming a semiconductor device comprising:
forming an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface;
forming a molding hole placed in the semiconductor substrate on the active region;
forming a pocket insulating layer pattern over the resulting structure to conformally cover the molding hole;
forming a pocket line extending across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate, the pocket line including a pocket conductive layer line, a lower metal layer line, and an upper metal layer line sequentially stacked on the pocket insulating layer pattern; and
forming a line capping layer pattern on the pocket line such that the line capping layer pattern and the pocket conductive layer line together surround the lower and upper metal layer lines.