Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines
View Patent ↗A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.
1. A single-rail multi-gate domino logic circuit driven by a multi-phase clock, comprising:
a first dynamic logic stage comprising a precharge clock circuit comprising two p-mosfet transistors respectively driven by separate phases of the multi-phase clock;
a second dynamic logic stage comprising an evaluate clock logic circuit comprising at least one n-mosfet transistor respectively driven by a separate phase of the multi-phase clock; and
dynamic gates directly coupled back-to-back at cell boundaries without an intervening static gate and the domino logic circuit performs a dynamic cascaded OR-precharge/domino-evaluate function.
2. A single-rail multi-gate domino logic circuit driven by a multi-phase clock, comprising:
a first dynamic logic stage comprising a precharge clock circuit comprising two p-mosfet transistors respectively driven by separate phases of the multi-phase clock;
a second dynamic logic stage comprising an evaluate clock logic circuit comprising at least one n-mosfet transistor respectively driven by a separate phase of the multi-phase clock; and
dynamic gates directly coupled back-to-back at cell boundaries without an intervening static gate and the domino logic circuit performs a dynamic cascaded domino-precharge/AND-evaluate function.
3. A single-rail multi-gate domino logic circuit driven by a multi-phase clock, comprising:
a first dynamic logic stage comprising a precharge clock circuit comprising at least one p-mosfet transistor respectively driven by a separate phase of the multi-phase clock;
a second dynamic logic stage comprising an evaluate clock logic circuit comprising at least one n-mosfet transistor respectively driven by a separate phase of the multi-phase clock; and
a secondary precharge network comprising at least one p-mosfet transistor respectively driven by the separate phase of the multi-phase clock.
4. The domino logic circuit of claim 3 wherein the first dynamic logic stage comprises two p-mosfet transistors driven by separate phases of the multi-phase clock.
5. The domino logic circuit of claim 3 wherein the second dynamic logic stage comprises two n-mosfet transistors driven by separate phases of the multi-phase clock.
6. The domino logic circuit of claim 3 wherein:
the first dynamic logic state performs any one of:
an OR-precharge function;
a domino-precharge function; and
the second dynamic logic stage performs any one of:
an AND-evaluate function;
an OR-evaluate function; and
a domino-evaluate function.
7. A single-rail multi-gate domino logic circuit driven by a multi-phase clock, comprising:
a first dynamic logic stage comprising a precharge clock circuit comprising two p-mosfet transistors respectively driven by separate phases of the multi-phase clock;
a second dynamic logic stage comprising an evaluate clock logic circuit comprising at least one n-mosfet transistor respectively driven by a separate phase of the multi-phase clock; and
a secondary precharge network comprising two p-mosfet transistors respectively driven by the separate phases of the multi-phase clock.