Wide frequency range delay locked loop
View Patent ↗A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
1. A delay locked loop comprising:
a digital delay circuit configured to enable digital delay elements in providing coarse phase adjustment during initialization in the delay locked loop;
a counter configured to control what number of the digital delay elements are enabled, and the counter being further configured to have an initial value which corresponds to an at least substantially minimum delay of the digital delay circuit; and
an analog delay circuit configured to provide, after the coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop, and the analog delay circuit being further configured to employ a variable control signal during the fine phase adjustment, and the analog delay circuit being further configured to receive a fixed control signal while the digital delay circuit provides the coarse phase adjustment.
2. The delay locked loop according to claim 1 wherein the counter is an up-counter.
3. The delay locked loop according to claim 1 wherein the counter is controlled by an input clock signal.
4. The delay locked loop according to claim 3 wherein the counter increments in response to rising edges of the input clock signal.
5. The delay locked loop according to claim 1 wherein the counter is implemented as a ripple counter.
6. The delay locked loop according to claim 1 wherein the counter is at ‘0’ upon reset.
7. The delay locked loop according to claim 1 wherein a maximum count of the counter corresponds to a sum total of the digital delay elements.
8. The delay locked loop according to claim 1 wherein the analog delay circuit is distinct from and in series with the digital delay circuit.
9. The delay locked loop according to claim 1 wherein the digital delay circuit operates over a wide delay range.
10. The delay locked loop according to claim 9 wherein the analog delay circuit operates over a small delay range within the wide delay range.
11. The delay locked loop according to claim 1 wherein the counter is configured to be disabled upon detection of an alignment between edges of clock signals.
12. The delay locked loop according to claim 11 wherein one of the clock signals is an internal clock signal.
13. The delay locked loop according to claim 1 wherein after the coarse phase adjustment is completed and while the fine phase adjustment is carried out in the delay locked loop, the digital delay circuit is configured to be held at a fixed delay.
14. The delay locked loop according to claim 1 , wherein when a delay limit of the analog delay circuit is approached during the fine phase adjustment, the digital delay circuit is allowed to enable or disable an additional digital delay element of the digital delay circuit.
15. A method for performing phase adjustment in a delay locked loop comprising:
initializing a counter to a value which corresponds to an at least substantially minimum delay of a digital delay circuit in the delay locked loop, and the counter controlling what number of digital delay elements of the digital delay circuit are enabled;
enabling the digital delay elements to provide coarse phase adjustment in the delay locked loop during initialization; and
providing, after the coarse phase adjustment is completed, a fine phase adjustment with an analog delay circuit in the delay locked loop, and the analog delay circuit:
i) employing a variable control signal during the fine phase adjustment; and
ii) receiving a fixed control signal while the digital delay circuit provides the coarse phase adjustment.
16. The method according to claim 15 further comprising controlling the counter by an input clock signal received by the counter.
17. The method according to claim 16 wherein the counter increments in response to rising edges of the input clock signal.
18. The method according to claim 15 wherein the counter is implemented as a ripple counter.
19. The method according to claim 15 further comprising resetting the counter to ‘0’, the resetting occurring before the enabling of the digital delay elements.
20. The method according to claim 15 further comprising:
detecting completion of the coarse phase adjustment;
freezing the course phase adjustment upon the completion; and
enabling the fine phase adjustment upon the freezing.
21. The method according to claim 15 further comprising:
after the coarse phase adjustment is completed and during the providing of the fine phase adjustment, holding the digital delay circuit at a fixed delay.
22. The method according to claim 15 wherein when a delay limit of the analog delay circuit is approached during the fine phase adjustment, the digital delay circuit is allowed to enable or disable an additional digital delay element of the digital delay circuit.