Low leakage and data retention circuitry
View Patent ↗An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
1. An integrated circuit comprising:
two power supply terminals for powering of the integrated circuit, said power supply terminals including a V dd positive supply terminal and a V ss ground terminal together defining a range of logic levels;
cells in series with a sleep transistor electrically connected to one of said power supply terminals, each of said cells being either a logic gate or a storage cell;
generator circuitry configured to generate a variable voltage outside said range of logic levels; and
additional circuitry configured to apply, in a power down mode, said variable voltage to said sleep transistor.
2. The integrated circuit as claimed in claim 1 wherein said one of the power supply terminals is the V ss terminal, said variable voltage outside the range of logic levels is a voltage lower than V ss , and said sleep transistor is an n-channel transistor.
3. The integrated circuit as claimed in claim 2 wherein said additional circuitry applies V dd to said sleep transistor when in another mode than said power down mode.
4. The integrated circuit as claimed in claim 2 wherein said additional circuitry applies a voltage greater than V dd to said sleep transistor when in another mode than said power down mode.
5. The integrated circuit as claimed in claim 1 wherein said one of the power supply terminals is the V dd terminal, said variable voltage is a voltage higher than V dd , and said sleep transistor is a p-channel transistor.
6. The integrated circuit as claimed in claim 5 wherein said additional circuitry applies V ss to said sleep transistor when not in a power down mode.
7. The integrated circuit as claimed in claim 5 wherein said additional circuitry applies a voltage less than V ss to said sleep transistor when not in a power down mode.
8. The integrated circuit as claimed in claim 1 wherein said cells include inverters.
9. The integrated circuit as claimed in claim 1 wherein said cells include flip-flops.
10. The integrated circuit as claimed in claim 1 wherein said sleep transistor has a similar gate thickness as transistors in said cells.
11. The integrated circuit as claimed in claim 10 wherein said sleep transistor and said transistors in said cells are thin gate devices.
12. The integrated circuit as claimed in claim 1 wherein said additional circuitry applies the voltage from a first of the power supply terminals to said sleep transistor when in another mode than said power down mode.
13. The integrated circuit as claimed in claim 1 wherein said generator circuitry comprises a sleep generator.
14. The integrated circuit as claimed in claim 13 wherein said sleep generator comprises a charge pump circuit.
15. The integrated circuit as claimed in claim 1 wherein said sleep transistor has a similar threshold voltage as transistors in said cells.
16. The integrated circuit as claimed in claim 15 wherein said sleep transistor is a regular threshold voltage transistor.
17. A power management method comprising:
operating an integrated circuit having cells, each of the cells being a either a logic gate or a storage cell, said cells being in series with a sleep transistor electrically connected to a either a V dd positive supply terminal or a V ss ground terminal, the V dd ' positive supply terminal and the V ss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including:
generating a variable voltage outside said range of logic levels; and
applying, in a power down mode, said variable voltage to the sleep transistor.
18. The power management method as claimed in claim 17 wherein the terminal is the V ss terminal, said variable voltage outside the range of logic levels is a voltage lower than V ss , and said sleep transistor is an n-channel transistor.
19. The power management method as claimed in claim 18 wherein said operating of the integrated circuit further includes applying V dd to said sleep transistor when in another mode than said power down mode.
20. The power management method as claimed in claim 18 wherein said operating of the integrated circuit further includes applying a voltage greater than V dd to said sleep transistor when in another mode than said power down mode.