Granted Patent B2

US 8,383,514 · App. 13/046,197 · Granted Feb 26, 2013

Abstract

Claims (80)

1. A method for stacking chips to form a serially-connected integrated circuit, the chips having substantially identical pad arrangement and placement, the method comprising:

creating chip via holes through each of first and second chips;

disposing an insulation layer in the chip via holes;

disposing a conductor in the chip via holes to create through-via connections; and

placing the second chip on top of the first chip to form a stacked pair of integrated circuit chips,

the first and second chips being arranged such that:

a transistor bearing surface of the first chip faces away from the second chip and a transistor bearing surface of the second chip faces away from the first chip; and

at least one series connection between a signal pad of the first chip and a signal pad of the second chip is formed by the through-via connections.

2. The method of claim 1 wherein creating the chip via holes comprises creating a through-chip and through-pad via hole to facilitate a connection between an output signal pad of the first chip and a corresponding input signal pad of the second chip.

3. The method of claim 1 further comprising:

depositing an insulation layer on the transistor bearing surface of the first chip;

forming contact holes in the insulation layer to permit connection to signal pads of the first chip;

depositing a conductor into the contact holes;

etching a conductor layer to remove excess conductor material from the portions outside the contact holes; and

attaching a second stacked pair of integrated circuit chips to the first chip of the stacked pair of integrated circuit chips to form a multi-chip circuit for a multi-chip package, the second stacked pair of integrated circuit chips being substantially identical to the first stacked pair of integrated circuit chips.

4. The method of claim 3 further comprising:

providing a memory controller for controlling access to the plurality of substantially identical chips;

connecting input signal pads of the multi-chip circuit to an output side of the controller; and

connecting output signal pads of the multi-chip circuit to an input side of the controller.

5. A method of fabricating a multi-chip device, comprising:

forming at least two stacked pairs of integrated circuit chips including a last stacked pair, comprising, for each stacked pair:

creating chip via holes through each of first and second chips;

disposing an insulation layer in the chip via holes;

disposing a conductor in the chip via holes to create through-via connections; and

placing the second chip on top of the first chip to form a stacked pair of integrated circuit chips,

the first and second chips being arranged such that:

a transistor bearing surface of the first chip faces away from the second chip and a transistor bearing surface of the second chip faces away from the first chip; and

at least one series connection between a signal pad of the first chip and a signal pad of the second chip is formed by the through-via connections;

forming a multi-chip circuit, comprising, for each stacked pair other than the last stacked pair:

depositing an insulation layer on top of the stacked pair of integrated circuit chips;

forming contact holes in the insulation layer to permit connection between certain adjacent signal pads when another chip is later placed on top;

depositing a conductor into the contact holes;

etching a conductor layer to remove excess conductor material from the portions outside the contact holes; and

attaching a next stacked pair on top of the stacked pair of integrated circuit chips to form a multi-chip circuit; and

adding wire bonding for connecting input signal pads of the multi-chip circuit to an output side of a controller and to connect output signal pads of the multi-chip circuit to an input side of the controller.

6. The method of claim 5 , further comprising covering the entire package or compound.

7. A multi-chip device including a stacked pair of integrated circuit chips comprising:

a first chip having:

at least one input signal pad for connection to at least one external input signal; and

at least one output signal pad symmetrically disposed about the center line of the first chip with respect to the at least one input signal pad;

a second chip having a substantially identical signal pad arrangement as the first chip, the second chip being flipped in orientation with respect to the first chip; and

at least one serial connection through-chip via connecting the at least one output signal pad of the first chip in series with the at least one input signal pad of the second chip.

8. The device of claim 7 wherein the at least one input signal pad and the at least one output signal pad are disposed along a single edge of the first chip.

9. The device of claim 8 wherein the single edge of the first chip lines up vertically with a corresponding edge of the second chip.

10. The device of claim 7 wherein:

the at least one input signal pad of the first chip is disposed on a first side of the center line of the first chip; and

the at least one output signal pad of the first chip is disposed on a second side of the center line of the first chip opposite the first side.

11. The device of claim 7 wherein the first chip and the second chip are aligned so there is substantially no offset.

12. The device of claim 7 wherein the at least one output signal pad of the first chip is in substantial alignment with the at least one input signal pad of the second chip.

13. A multi-chip device comprising:

a plurality of substantially identical chips arranged in a stack, the plurality of chips including a first chip, an even number of intermediate chips and a last chip, each chip comprising:

one or more input signal pads; and

one or more output signal pads symmetrically disposed about a center line of the chip with respect to respective input signal pads;

the input signal pads of each intermediate chip being serially connected to corresponding output signal pads of a first adjacent chip by one or more first serial connections;

the output signal pads of each intermediate chip being serially connected to corresponding input signal pads of a second adjacent chip by one or more second serial connections;

one of the first serial connections and second serial connections comprising through-chip vias,

the other of the first serial connections and the second serial connections comprising signal pads;

the input signal pads of the first chip being serially connected to one or more external input signals;

the output signal pads of the first chip being serially connected to corresponding output signal pads of an adjacent chip by one or more serial connections comprising through-chip vias;

the input signal pads of the last chip being serially connected to corresponding output signal pads of an adjacent chip by one or more serial connections comprising through-chip vias;

the output signal pads of the last chip being serially connected to one or more external output signals;

the plurality of substantially identical chips being provided in a stack, each alternating chip in the stack being flipped in orientation with respect an adjacent chip.

14. The device of claim 13 further comprising an insulator disposed between pads of adjacent intermediate chips to prevent contact between selected adjacent pads.

15. The device of claim 14 further comprising a through-pad via extending through the insulator to connect the one or more output signal pads of one of the intermediate chips to respective one or more input signal pads of an adjacent intermediate chip.

16. The device of claim 14 further comprising:

a controller for controlling access to the plurality of substantially identical chips;

controller input connections to connect output signal pads from the last chip to an input side of the controller; and

controller output connections to connect an output side of the controller to the input pads of the first chip.

17. The device of claim 16 wherein the controller is placed below the stacked chips, and the controller output connections comprise wire bonding.

18. The device of claim 16 wherein the controller is placed above the stacked chips, and the controller input connections comprise wire bonding.

19. A multi-chip device comprising:

a plurality of substantially identical chips including a first chip, an even number of intermediate chips and a last chip, each chip in the device having substantially identical signal pad arrangements, the plurality of chips being provided in a stack, each alternating chip in the stack being flipped in orientation with respect to an adjacent chip;

at least one serial through-chip via; and

at least one serial connection between output and input signal pads of two of the intermediate chips.

20. A multi-chip package comprising:

a plurality of substantially identical chips including a first chip, an even number of intermediate chips and a last chip, each chip in the device having substantially identical signal pad arrangements, the plurality of chips being provided in a stack, each alternating chip in the stack being flipped in orientation with respect an adjacent chip;

at least one serial through-chip via;

at least one serial connection between output and input signal pads of two of the intermediate chips;

package input connectors for connection to external input signals; and

package output connectors for connection to external output signals.

Assignments (12)