Charge pump for PLL/DLL
View Patent ↗A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
1. A charge pump comprising:
pull-up circuitry configured to generate pull-up current to increase voltage at a charge pump output, the pull-up circuitry comprising a current source and a controlled transistor having a gate adapted for connection to a first input signal for being controlled thereby, the pull-up circuitry connected between a positive voltage supply and a charge pump output node;
pull-down circuitry configured to generate pull-down current to decrease voltage at the charge pump output, the pull-down circuitry comprising a current source and a controlled transistor having a gate adapted for connection to a second input signal for being controlled thereby, the pull-down circuitry connected between a ground voltage supply and the charge pump output node, and the first and second input signals being derived from up and down signals, respectively;
an operation amplifier having two inputs and an output, the operational amplifier configured to reduce phase error, one of the inputs of the operational amplifier connected to the charge pump output node; and
a reference current source having a plurality of select transistors and a plurality of mirror master transistors, the mirror master transistors coupled to slave transistors of either the pull-up circuitry or the pull-down circuitry to mirror variable current in the slave transistors.
2. The charge pump of claim 1 wherein the current sources in each of the pull-up circuitry and the pull-down circuitry comprises a transistor connected in series with the respective controlled transistor.
3. The charge pump of claim 2 wherein the controlled transistor in the pull-up circuitry is connected to the positive voltage supply, and the current source transistor in the pull-up circuitry is connected to the charge pump output node.
4. The charge pump of claim 2 wherein the controlled transistor in the pull-down circuitry is connected to the ground voltage supply, and the current source transistor in the pull-down circuitry is connected to the charge pump output node.
5. The charge pump of claim 1 further comprising additional pull-up circuitry and additional pull-down circuitry connected together at an additional node.
6. The charge pump of claim 5 wherein the additional pull-up circuitry and the pull-up circuitry have corresponding transistors with source and drain terminals connected in the same manner, and the additional pull-down circuitry and the pull-down circuitry have corresponding transistors with source and drain terminals connected in the same manner.
7. The charge pump of claim 6 wherein a gate of a controlled transistor in the additional pull-up circuitry is connected to a first voltage supply, and a gate of a controlled transistor in the additional pull-down circuitry is connected to a second voltage supply.
8. The charge pump of claim 6 wherein the additional pull-up circuitry and the pull-up circuitry have correspondingly same sized transistors, and the additional pull-down circuitry and the pull-down circuitry have correspondingly same sized transistors.
9. The charge pump of claim 5 wherein the other input of the operational amplifier is connected to the additional node.
10. The charge pump of claim 9 wherein the output of the operational amplifier is connected to one of the current source of the pull-down circuitry and the current source of the pull-up circuitry, and the reference current source is connected to the current source of the other circuitry.
11. The charge pump of claim 1 wherein the operational amplifier has an output range substantially from rail to rail.
12. The charge pump of claim 1 wherein the operational amplifier comprises two differential input stages.
13. The charge pump of claim 12 wherein the differential input stages comprise one PMOS input differential stage and one NMOS input differential stage.
14. The charge pump of claim 1 wherein the charge pump output node is connected to a voltage controlled oscillator to form part of a phase locked loop.
15. The charge pump of claim 1 wherein the charge pump output node is connected to a voltage controlled delay line to form part of a delay locked loop.
16. The charge pump of claim 1 further comprising registers coupled to the plurality of select transistors.
17. The charge pump of claim 1 further comprising fuses coupled to the plurality of select transistors.
18. The charge pump of claim 1 wherein the plurality of select transistors and the plurality of mirror master transistors include a programmable array of field-effect transistors.