Bridge device architecture for connecting discrete memory devices to a system
View Patent ↗Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.
1. A bridge device to access a discrete memory device in response to first signals having a global format, the bridge device comprising:
an input/output interface of the bridge device to communicate the first signals having the global format to and from the bridge device; and
a device interface of the bridge device to communicate second signals having a local format between the bridge device and the discrete memory device, the second signals corresponding in function to the first signals and having a local format different from the global format.
2. The bridge device of claim 1 , wherein the device interface includes a local input/output port connected to the discrete memory device to communicate the second signals.
3. The bridge device of claim 1 , wherein the input/output interface includes a global input port for receiving the first signals, and a global output port for providing one of the first signals and read data from the discrete memory device.
4. The bridge device of claim 1 , further comprising:
a format converter to convert the first signals having the global format to the second signals having the local format and to convert the second signals having the local format to the first signals having the global format.
5. The bridge device of claim 4 , wherein the first signals includes global commands and global command signals, and the format converter includes a command format converter to convert the global commands and the global command signals in the first signals having the global format to the local format.
6. The bridge device of claim 4 , wherein the format converter includes a data format converter to convert data between the global format and the local format.
7. The bridge device of claim 6 , wherein the first signals are received in a global command, the global command further including an address header.
8. The bridge device of claim 7 , wherein the address header includes a global device address corresponding to a selected composite memory device and a local device address corresponding to a selected discrete memory device of an at least one discrete memory device in the selected composite memory device.
9. The bridge device of claim 1 , wherein the global format includes a serial data interface format and the local format includes an asynchronous flash memory format.
10. The bridge device of claim 1 , wherein the global format includes an ONFi specification interface format and the local format includes an asynchronous flash memory format.
11. A memory system comprising:
a memory controller for providing a global command corresponding to a memory operation;
n composite memory devices connected in parallel with each other and the memory controller, each of the n composite memory devices having m discrete memory devices and a bridge device, the bridge device of a selected composite memory device of the n composite memory devices to receive the global command for providing local memory control signals corresponding to the memory operation to a selected discrete memory device of the m discrete memory devices, where n and m are integer values greater than 0.
12. The memory system of claim 11 , wherein each of the n composite memory devices has a clock port for receiving a clock signal and a plurality of data input/output ports for receiving commands and write data, and for providing read data.
13. The memory system of claim 11 , wherein the memory system is a homogeneous memory system.
14. The memory system of claim 11 , wherein the memory system is a heterogeneous memory system.
15. The memory system of claim 11 , wherein the m discrete memory devices of each of the n composite memory devices are flash memory devices.
16. The memory system of claim 11 , wherein the m discrete memory devices of each of the n composite memory devices are asynchronous flash memory devices.
17. A semiconductor chip to access a discrete memory chip in response to first signals having a global format, the semiconductor chip comprising:
an input/output interface to communicate the first signals having the global format to and from the semiconductor chip; and
a memory device interface to communicate second signals having a local format between the semiconductor chip and the discrete memory chip, the second signals corresponding in function to the first signals and having a local format different from the global format.
18. The semiconductor chip of claim 17 , wherein the memory device interface includes a local input/output port connected to the discrete memory chip to communicate the second signals.
19. The semiconductor chip of claim 17 , wherein the input/output interface includes a global input port for receiving the first signals, and a global output port for providing one of the first signals and read data from the discrete memory chip.
20. The semiconductor chip of claim 17 , further comprising: a format converter to convert the first signals having the global format to the second signals having the local format and to convert the second signals having the local format to the first signals having the global format.
21. The semiconductor chip of claim 20 , wherein the first signals includes global commands and global command signals, and the format converter includes a command format converter to convert the global commands and the global command signals in the first signals having the global format to the local format.
22. The semiconductor chip of claim 20 , wherein the format converter includes a data format converter to convert data between the global format and the local format.
23. The semiconductor chip of claim 22 , wherein the first signals are received in a global command, the global command further including an address header.
24. The semiconductor chip of claim 23 , wherein the address header includes a global device address corresponding to a selected composite memory device and a local device address corresponding to a selected discrete memory chip of an at least one discrete memory chip in the selected composite memory device.
25. The semiconductor chip of claim 17 , wherein the global format includes a serial data interface format and the local format includes an asynchronous flash memory format.