Granted Patent B2

US 7,903,477 · App. 12/181,115 · Granted Mar 8, 2011

Abstract

Claims (72)

1. A system comprising:

a voltage generator circuit to produce a pre-charge voltage signal for pre-charging at least one signal in a memory circuit;

an input configured to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator circuitry, the input indicating whether the memory circuit is set to a power-saving mode; and

wherein the input indicates to adjust a magnitude of the pre-charge voltage signal during the power-saving mode to reduce a voltage difference between the pre-charge voltage signal and a voltage of the at least one signal.

2. The system as in claim 1 further comprising:

a voltage adjustor circuit to receive the input, the voltage adjustor circuit configured to increase a magnitude of the pre-charge voltage signal when the memory circuit is set to the power-saving mode.

3. The system as in claim 1 , wherein the at least one signal includes a data bus signal in the memory circuit used for accessing data stored in cells of the memory circuit.

4. The system as in claim 1 , wherein the power-saving mode is a deep power down mode during which the memory circuit is powered but during which no data can be accessed from the memory circuit.

5. The system as in claim 1 , wherein the at least one signal is set to a logic high state during the power-saving mode; and

wherein the pre-charge voltage signal is increased from a first voltage, which is used for pre-charging the at least one signal during a non power-saving mode, to a second voltage during the power-saving mode, the second voltage being nearer in voltage value to the logic high state than to the first voltage.

6. The system as in claim 1 , wherein the voltage generator circuit and memory circuit reside in a mobile communications device, the input specifying when the mobile communications device is in a deep power-saving mode during which cells in the memory circuit do not retain stored data.

7. A system comprising:

a voltage generator circuit to produce a pre-charge voltage signal for pre-charging at least one signal in a memory circuit; and

an input configured to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator circuitry, the input indicating whether the memory circuit is set to a power-saving mode;

a voltage adjustor circuit to receive the input, the voltage adjustor circuit configured to increase a magnitude of the pre-charge voltage signal when the memory circuit is set to the power-saving mode;

wherein the voltage adjustor circuit includes at least one field effect transistor to electrically couple the pre-charge voltage signal to a higher voltage level than a voltage level of the pre-charge voltage signal as produced by the voltage generator circuit when the memory circuit is in a non-power saving mode.

8. A system comprising:

a voltage generator circuit to produce a pre-charge voltage signal for pre-charging at least one signal in a memory circuit;

an input configured to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator circuitry, the input indicating whether the memory circuit is set to a power-saving mode;

switch circuitry configured to selectively couple the pre-charge voltage signal to the at least one signal in the memory circuit; and

wherein the input indicates that the memory circuit is set to the power-saving mode, the input causing the voltage generator circuit to adjust the magnitude of the pre-charge voltage during the power-saving mode to reduce leakage of current on a path from the pre-charge voltage signal through the switch circuit to the at least one signal in the memory circuit.

9. A system comprising:

a voltage generator circuit to produce a pre-charge voltage signal for pre-charging at least one signal in a memory circuit;

an input configured to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator circuitry, the input indicating whether the memory circuit is set to a power-saving mode;

switch circuitry configured to, during the power-saving mode, decouple the pre-charge voltage signal from the at least one signal in the memory circuit;

a driver circuit configured to drive the at least one signal; and

a current leakage path extending from the driver circuit along the at least one signal through a respective switch of the switch circuitry to the voltage generator circuit, the respective switch being oriented in the leakage path such that a first node of the switch is in electrical communication with the at least one data bus signal and a second node of the switch is in electrical communication with the pre-charge voltage signal produced by the voltage generator circuit.

10. The system as in claim 9 , wherein the input indicates, during the power-saving mode, to adjust the pre-charge voltage signal to a voltage value nearer a voltage value of the at least one signal during the power-saving mode; and

wherein the input indicates, at times other than during the power-saving mode, to set the pre-charge voltage signal to an intermediate level between a high logic state and low logic state applied to the at least one signal by the driver circuit.

11. A voltage generator circuit comprising:

an input specifying a mode setting of a memory circuit; and

an output:

the output being set to a first voltage for pre-charging at least one data bus signal in the memory circuit during a first mode setting in which cells in the memory circuit are accessible,

the output being set to a second voltage during a second mode setting in which the cells in the memory circuit are inaccessible.

12. The voltage generator circuit as in claim 11 , wherein the at least one data bus signal is driven to different logic states during the first mode setting; and

wherein the at least one data bus signal is driven to a single predetermined logic state during the second mode setting.

13. The voltage generator circuit as in claim 12 , wherein the different logic states include a logic high state and a logic low state; and

wherein a magnitude of the first voltage falls in an intermediate range between the logic high state and the logic low state, the first voltage being used to pre-charge the at least one data bus signal for a memory access; and

wherein the second voltage is nearer in value to one of the logic high state and the logic low state than to the first voltage value.

14. The voltage generator circuit as in claim 11 , wherein the second voltage is nearer in magnitude to one of a logic high state and logic low state than to the first voltage.

15. The voltage generator circuit as in claim 11 , wherein the second mode setting is a power-saving mode as compared to the first mode setting, the first mode setting being a non power-saving mode in which the memory circuit retains data.

16. The voltage generator circuit as in claim 11 , wherein the first voltage is used to pre-charge the at least one data bus for accessing the cells in the memory circuit during the first mode setting; and

wherein the second voltage is used to reduce energy consumption during the second mode setting.

17. The voltage generator circuit as in claim 11 , wherein the at least one data bus includes a differential data bus pair including a first data bus signal and a second data bus signal, both of which are repeatedly pre-charged to the first voltage during the first mode setting for accessing the cells in the memory circuit; and

wherein, during the second mode setting, the first data bus signal and the second data bus signal are isolated from the second voltage via at least one electronic switch set to an OFF state.

18. The voltage generator circuit as in claim 11 , wherein a driver circuit is configured to drive the at least one data bus to a predetermined logic state during the second mode setting; and

wherein the second mode setting provides reduced power consumption as a result of changing the output from the first voltage to the second voltage.

19. The voltage generator circuit as in claim 18 , wherein a voltage difference between the second voltage and the predetermined logic state is less than a voltage difference between the first voltage and the predetermined logic state.

20. The voltage generator circuit as in claim 11 , wherein the output is selectively coupled by a switch circuit to the at least one data bus during the first mode setting to enable pre-charging of the at least one data bus; and

wherein the output is set to the second voltage in lieu of the first voltage during the second mode setting to reduce a leakage of current from the at least one data bus through the switch circuit to the output.

21. A method comprising:

receiving an input specifying a mode setting of a memory circuit;

producing an output;

setting the output to a first voltage for pre-charging at least one data bus signal in the memory circuit during a first mode in which cells in the memory circuit are accessible; and

setting the output to a second voltage during a second mode in which the cells in the memory circuit are inaccessible.

22. The method as in claim 21 further comprising:

driving the at least one data bus signal to different logic states during the first mode; and

driving the at least one data bus signal to a single predetermined logic state during the second mode.

23. The method as in claim 22 , wherein the different logic states include a logic high state and a logic low state, the method further comprising:

setting a magnitude of the first voltage to an intermediate voltage between the logic high state and the logic low state to pre-charge the at least one data bus signal for performing a memory access; and

setting the second voltage nearer in value to one of the logic high state and the logic low state than to the first voltage.

24. The method as in claim 21 further comprising:

setting the output to the second voltage, which is nearer in magnitude to one of the different logic states than to the first voltage.

25. The method as in claim 21 further comprising:

utilizing the first voltage to pre-charge the at least one data bus for accessing the cells in the memory circuit during the first mode; and

switching from outputting the first voltage to outputting the second voltage to reduce power consumption during the second mode.

26. The method as in claim 21 further comprising:

driving the at least one data bus to a predetermined logic state during the second mode setting; and

wherein a voltage difference between the second voltage and the predetermined logic state is less than a voltage difference between the first voltage and the predetermined logic state.

27. The method as in claim 21 further comprising:

initiating operation of a switch circuit to couple the output to the at least one data bus during the first mode to pre-charge the at least one data bus; and

during the second mode, setting the output to the second voltage in lieu of the first voltage to reduce a leakage of current from the output through the switch circuit to the at least one data bus.

Assignments (10)