Start up circuit for delay locked loop
View Patent ↗An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.
1. An apparatus comprising:
first and second latches; and
a circuit configured to enable the first and second latches in response to a reset signal, the circuit comprising:
a first arrangement of a plurality of stages, each stage having a storage element clocked by a first clock signal, an output of the first arrangement electrically connected to the first latch; and
a second arrangement of a plurality of stages, each stage having a storage element clocked by a second clock signal, the second arrangement receiving the output of the first arrangement, an output of the second arrangement electrically connected to the second latch.
2. The apparatus of claim 1 , wherein the first arrangement, in response to the reset signal, enables the first latch after a delay corresponding to the number of stages of the first arrangement.
3. The apparatus of claim 2 , wherein the delay is a duration of at least a number of clock cycles of the first clock signal corresponding to one less than the number of stages of the first arrangement.
4. The apparatus of claim 1 , wherein the second arrangement in response to the reset signal, enables the second latch after a delay corresponding to the number of stages of the first arrangement and the second arrangement.
5. The apparatus of claim 4 , wherein the delay is a duration of at least 1) a number of clock cycles of the first clock signal corresponding to one less than the number of stages of the first arrangement, and 2) a number of clock cycles of the second clock signal corresponding to one less than the number of stages of the second arrangement.
6. The apparatus of claim 1 , wherein the frequencies of the first and second clock signals are substantially equal.
7. The apparatus of claim 1 , wherein the storage elements each include a latch.
8. The apparatus of claim 7 , wherein the latches of successive stages are electrically connected via a respective output and a respective input.
9. The apparatus of claim 1 , wherein the first latch is clocked by the second clock signal, and the second latch is clocked by the first clock signal.
10. The apparatus of claim 1 , wherein the first latch generates a control signal responsive to the second clock signal, and the second latch generates a control signal responsive to the first clock signal.
11. An apparatus comprising:
first and second latches; and
a circuit configured to enable the first and second latches in response to a reset signal, the circuit comprising:
a first arrangement of a plurality of stages, each stage having a latch clocked by a reference clock signal, an output of the first arrangement electrically connected to the first latch; and
a second arrangement of a plurality of stages, each stage having a latch clocked by a feedback clock signal, the second arrangement receiving the output of the first arrangement, an output of the second arrangement electrically connected to the second latch.