Method and apparatus for synchronization of row and column access operations
View Patent ↗A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.
1. A semiconductor memory device having bitline sense amplifiers, memory cells and column access devices connected to bitlines, comprising:
a wordline connected to the memory cells and asserted in response to a wordline timing pulse;
sense enable circuitry for enabling the bitline sense amplifiers during the wordline timing pulse;
column decoders for enabling the column access devices during the wordline timing pulse; and
delay circuitry for enabling the column decoders and the sense enable circuitry at different times in response to the wordline timing pulse.
2. The semiconductor memory device of claim 1 , wherein the delay circuitry includes
a delay circuit delaying the wordline timing pulse to provide a delayed wordline timing pulse, and
a logic circuit logically combining the delayed wordline timing pulse with the wordline timing pulse to provide a sense enable signal for enabling the sense enable circuitry before the column decoders are enabled.
3. The semiconductor memory device of claim 1 , wherein the delay circuitry includes
a delay circuit for receiving a delayed version of the wordline timing pulse to provide a further delayed wordline timing pulse, and
a logic circuit logically combining the further delayed wordline timing pulse with the wordline timing pulse to provide a column enable signal for enabling the column decoders after the sense enable circuitry is enabled.
4. The semiconductor memory device of claim 2 , wherein
the delay circuit comprises a first delay circuit and the logic circuit comprises a first logic circuit, and the delay circuitry further includes
a second delay circuit delaying the delayed wordline timing pulse to provide a further delayed wordline timing pulse, and
a second logic circuit logically combining the further delayed wordline timing pulse with the wordline timing pulse to provide a column enable signal for enabling the column decoders after the sense enable circuitry is enabled.
5. The semiconductor memory device of claim 2 , wherein
the delay circuit comprises a first delay circuit for providing the delayed wordline timing pulse after a first time delay, and the logic circuit comprises a first logic circuit, and the delay circuitry further includes
a second delay circuit delaying the wordline timing pulse by a second time delay to provide a further delayed wordline timing pulse, and
a second logic circuit logically combining the further delayed wordline timing pulse with the wordline timing pulse to provide a column enable signal for enabling the column decoders after the sense enable circuitry is enabled.
6. The semiconductor memory device of claim 5 , wherein the second time delay is greater than the first time delay.
7. The semiconductor memory device of claim 2 , wherein the sense enable circuitry drives a sense amplifier power supply line to a positive voltage level in response to the sense enable signal.
8. The semiconductor memory device of claim 7 , wherein the delay circuitry includes
column logic circuitry for providing a column enable signal that enables the column decoders in response to the sense amplifier power supply line exceeding a predetermined voltage level.
9. The semiconductor memory device of claim 8 , further including a comparator for sensing the predetermined voltage level of the sense amplifier power supply line, and for providing an output signal when the sense amplifier power supply line has exceeded the predetermined voltage level, the output signal being received by the column logic circuitry to provide the column enable signal in response to the wordline timing pulse.
10. The semiconductor memory device of claim 9 , further including a delay element for delaying the output signal.
11. The semiconductor memory device of claim 1 , further including a row decoder for driving the wordline in response to the wordline timing pulse and a predecoded row address.
12. The semiconductor memory device of claim 1 , wherein the column decoders receive predecoded column addresses for selectively enabling the column access devices during the wordline timing pulse.
13. A method for operating a semiconductor memory device having bitline sense amplifiers, memory cells and column access devices connected to bitlines, the method comprising:
asserting a wordline connected to the memory cells in response to a wordline timing pulse;
enabling the bitline sense amplifiers during the wordline timing pulse after the wordline is driven to the active level; and,
enabling the column access devices during the wordline timing pulse after the bitline sense amplifiers are enabled.
14. The method of claim 13 , wherein asserting the wordline includes enabling a row decoder with the wordline timing pulse in combination with a predecoded row address.
15. The method of claim 13 , wherein enabling the bitline sense amplifiers includes delaying the wordline timing pulse by a first time period to provide a delayed wordline timing pulse.
16. The method of claim 15 , wherein enabling the bitline sense amplifiers further includes enabling sense enable circuitry in response to the delayed wordline timing pulse for driving a sense amplifier power supply line connected to the bitline sense amplifiers to a positive voltage level.
17. The method of claim 15 , wherein enabling the column access devices includes delaying the delayed wordline timing pulse by a second time period to provide a further delayed wordline timing pulse.
18. The method of claim 15 , wherein enabling the column access devices includes delaying the wordline timing pulse by a second time period greater than the first time period to provide a further delayed wordline timing pulse.
19. The method of claim 16 , wherein enabling the column access devices includes detecting a predetermined voltage level of the sense amplifier power supply line, and providing an output when the predetermined voltage level is detected.
20. The method of claim 19 , wherein enabling the column access devices includes providing a column select enable signal in response to the wordline timing pulse and the output.
21. The method of claim 19 , wherein enabling the column access devices further includes enabling column decoders with the column select enable signal to decode predecoded column addresses for selectively enabling the column access devices.
22. The method of claim 20 , including delaying the output by a second time period.