Method and system for accessing a flash memory device
View Patent ↗An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
1. A method of addressing at least one memory block in a flash memory device, comprising:
receiving a data stream at any one of a plurality of interfaces;
determining a flash memory block associated with the data stream; and
addressing the flash memory block from the any one of the plurality of interfaces.
2. The method of claim 1 , wherein determining the flash memory block associated with the data stream comprises decoding command data in the data stream to determine the flash memory block associated with the data stream.
3. The method of claim 1 , wherein receiving the data stream comprises receiving single-bit-wide data streams at any one of the plurality of interfaces.
4. The method of claim 1 , wherein decoding command data in the data stream comprises analyzing the data stream to determine a command word and at least one of a column, row or bank address word.
5. The method of claim 1 , further comprising:
receiving a further data stream at another of the plurality of interfaces;
decoding command data in the further data stream to determine a second flash memory block associated with the further data stream; and
addressing the second flash memory block while concurrently addressing the flash memory bank.
6. The method of claim 1 , further comprising transferring data to or from the flash memory block.
7. A flash memory device having at least one memory bank comprising:
a plurality of data link interfaces, each configured for receiving a data stream containing access data; and
a control module for determining a selected memory bank of the at least one memory bank associated with the data stream in response to information in the access data, and transfer data between any one of the plurality of data link interfaces and the selected memory bank.
8. The device of claim 7 , wherein each of the plurality of data link interfaces is configured for outputting one of the data stream and read data.
9. The device of claim 7 , wherein the data stream is a single-bit-wide data stream.
10. The device of claim 9 , wherein the access data includes a command, an address, and a memory bank identifier, the control module determining the selected memory bank in response to the memory bank identifier.
11. The device of claim 10 , wherein each of the plurality of data link interfaces includes a command interpreter for decoding the command.
12. The device of claim 10 , wherein each of the plurality of data link interfaces is configured for outputting read data from the selected memory bank in response to the command and the address, when the command corresponds to a read operation.
13. The device of claim 12 , wherein output data provided from the selected memory bank is provided in parallel, and each of the plurality of data link interfaces includes a parallel to serial circuit for converting the output data into the read data in a single-bit-wide data stream.
14. The device of claim 9 , wherein each of the plurality of data link interfaces includes a serial to parallel circuit for converting the single-bit-wide data stream into parallel data.
15. The device of claim 7 , wherein the control module includes a switch circuit for coupling one of the plurality of data link interfaces with the selected memory bank.
16. The device of claim 15 , wherein the switch circuit couples command information and address information of the access data received at any one of the plurality of data link interfaces to one of the selected memory bank and another memory bank.
17. The device of claim 16 , wherein the switch circuit couples the command information and the address information as parallel bits of data.
18. The device of claim 16 , wherein the switch circuit is controllable for coupling output data from one of the selected memory bank and another memory bank to any one of the plurality of data link interfaces.
19. The device of claim 16 , wherein the access data includes program data, and the switch circuit is controllable for coupling the program data from any one of the plurality of data link interfaces to one of the selected memory bank and another memory bank.