IP Library Granted Patent US 7,631,116
Granted Patent B2
US 7,631,116 · App. 11/257,525 · Granted Dec 8, 2009

Method and system for packet encryption

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Quick Facts
Patent No.
US 7,631,116
App. No.
11/257,525
Granted
Dec 8, 2009
Kind
B2
Abstract

A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

Claims (51)

1. A data processing system comprising:

a plurality of data processors;

a master processor for receiving a data packet and modifying the received data packet to include control data, the control data comprising a list of functions to be performed on the data packet; and

a controller, linked to the master processor through an interconnection of the data processing system, that:

responds to the control data in the data packet to determine a data processor of the plurality of data processors dedicated to performing a function in the list of functions; and

forwards the data packet with the control data to the determined data processor for performing the function in the list of functions to process the data packet.

2. The data processing system according to claim 1 , further comprising:

an output port for providing the processed data packet without the control data after completion of the list of functions to be performed in the data packet.

3. The data processing system according to claim 2 , wherein the interconnection comprises a data buffer, and wherein the data buffer interconnects the plurality of data processors, the master processor, the controller and the output port.

4. The data processing system according to claim 3 , wherein the data buffer comprises the controller.

5. The data processing system according to claim 3 , wherein the controller repeatedly forwards the data packet to different data processors of the plurality of data processors, each data processor returning the data packet to the data buffer after processing the data packet.

6. The data processing system according to claim 3 , wherein the data buffer supports bidirectional communications.

7. The data processing system according to claim 1 , wherein the controller further comprises a resource manager circuit for maintaining information on availability of the plurality of data processors.

8. The data processing system according to claim 1 , wherein the control data comprises a code to be processed in at least one of the plurality of data processors.

9. The data processing system according to claim 1 , wherein the control data comprises an encryption or authentication key.

10. The data processing system according to claim 1 , wherein the functions performed by the data processors comprise the function of adding result data to the control data.

11. The data processing system according to claim 1 , wherein the functions performed by the data processors comprise the function of performing Internet protocol security (IPSEC) protocol processing.

12. The data processing system according to claim 1 , wherein the functions performed by the data processors comprise the function of performing Internet protocol (IP) header manipulation and encryption.

13. The data processing system according to claim 1 , wherein the functions performed by the data processors comprise the function of performing authentication processing.

14. The data processing system according to claim 1 , wherein the master processor is reprogrammable.

15. The data processing system according to claim 1 , wherein at least a first data processor of the plurality of data processors performs a function related to encoding or decoding of the data packet, and wherein at least a second data processor of the plurality of data processors performs a function unrelated to encoding or decoding of the data packet.

16. A data processor comprising:

an input port for receiving packets of data;

a master processor connected to the input port, the master processor modifying the received packet of data to include a header comprising instructions to be performed to the packet of data and for providing the modified data packet to a buffer; and

a controller linked to the master processor through an interconnection of the data processor and acting on the buffer to provide the modified data packet to a processor within the plurality of processors in response to the header, the controller further acting on the buffer to provide the modified data packet to an output port.

17. A method of processing data packets in a plurality of interconnected data processors, the method comprising:

receiving a data packet at a master processor;

modifying at the master processor the received data packet to include control data including a list of functions to be performed on the data packet;

determining, at a controller linked to the master processor, and in response to the control data, a data processor from the plurality of interconnected data processors dedicated to performing a function in the list of functions; and

forwarding the data packet with the control data from processor to processor in the plurality of interconnected data processors for performing functions on the data packets.

18. The method of claim 17 , further comprising:

providing the processed data packet without the control data upon completion of the functions in the list of functions.

19. The method of claim 17 , wherein:

forwarding the data packet comprises forwarding the data packet from processor to processor in the plurality of interconnected data processors through a packet buffer included in the interconnection.

20. The method of claim 19 , wherein forwarding the data packet with the control data from processor to processor includes repeatedly forwarding the data packet to different data processors of the plurality of interconnected data processors, each data processor returning the data packet to the packet buffer after processing the data packet.

21. The method of claim 19 , wherein the packet buffer supports bidirectional communications.

22. The method of claim 17 , wherein:

determining a data processor comprises maintaining information on availability of the plurality of interconnected data processors.

23. The method of claim 17 , wherein:

modifying the received data packet comprises modifying the received data packet to include control data including code to be processed in at least one of the data processors.

24. The method of claim 17 , wherein:

modifying the received data packet comprises modifying the received data packet to include control data including an encryption or authentication key.

25. The method of claim 17 , further comprising:

adding result data to the control data in individual data processors.

26. The method of claim 17 , wherein the functions include:

performing Internet protocol security (IPSEC) protocol processing in the data processors.

27. The method of claim 17 , wherein the functions include:

performing Internet protocol (IP) header manipulation and encryption, in respective data processors.

28. The method of claim 17 , wherein the functions include:

performing authentication processing in each of the data processors.

29. The method of claim 17 , wherein at least a first data processor of the plurality of interconnected data processors performs a function related to encoding or decoding of the data packet, and wherein at least a second data processor of the plurality of interconnected data processors performs a function unrelated to encoding or decoding of the data packet.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
CHANGE OF ADDRESS Recorded Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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RELEASE OF SECURITY INTEREST Recorded Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
CHANGE OF NAME Recorded Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
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U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM Recorded Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
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TO CORRECT AN ERROR MADE IN A PREVIOUSLY RECORDED DOCUMENT THAT ERRONEOUSLY AFFECTS THE PATENT Recorded Sep 23, 2011
From: MOSAID TECHNOLOGIES INCORPORATED
To: MOSAID TECHNOLOGIES INCORPORATED
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2011
From: LOW, ARTHUR JOHN, MR.; DAVID, STEPHEN JAMES, MR.
To: CHRYSALIS-ITS INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2011
From: CHRYSALIS-ITS INC.
To: MOSAID TECHNOLOGIES INCORPORATED
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CHANGE OF REGISTERED OFFICE ADDRESS Recorded Sep 7, 2011
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