Port packet queuing
View Patent ↗A port queue includes a first memory portion having a first memory access time and a second memory portion having a second memory access time. The first memory portion includes a cache row. The cache row includes a plurality of queue entries. A packet pointer is enqueued in the port queue by writing the packet pointer in a queue entry in the cache row in the first memory. The cache row is transferred to a packet vector in the second memory. A packet pointer is dequeued from the port queue by reading a queue entry from the packet vector stored in the second memory.
1. A switch comprising:
an ingress port configured to receive data packets;
a segment buffer memory in communication with the ingress port and being configured to store the data packets received from the ingress port;
a plurality of egress ports, each egress port being in communication with the segment buffer memory and being configured to forward the data packets; and
a plurality of egress port queues, each egress port queue being configured to store pointers to the locations of respective ones of the stored data packets to be forwarded to at least one associated egress port of the plurality of egress ports, each egress port queue comprising:
a first queue memory having a first memory access time, the first queue memory being configured to store the pointers; and
a second queue memory having a second memory access time that is significantly slower than the first memory access time, the second queue memory being in communication with the first queue memory for receiving a plurality of pointers from the first queue memory in a single transfer cycle.
2. The switch of claim 1 , wherein the plurality of pointers are written as a linked list in the second queue memory.
3. The switch of claim 1 , wherein each pointer is dequeued from the egress port queue by reading the pointer from the second queue memory.
4. The switch of claim 1 , wherein the second queue memory is in communication with the first queue memory via intermediate logic.
5. The switch of claim 4 , wherein the intermediate logic is operative to:
read the plurality of pointers from the first queue memory; and
write the plurality of pointers to the second queue memory in a single transfer cycle.
6. The switch of claim 5 , wherein the intermediate logic reads the plurality of pointers from the first queue memory when a number of pointers stored in the first queue memory is greater than a predetermined threshold.
7. The switch of claim 5 , wherein the intermediate logic reads the plurality of pointers from the first queue memory when at least one row of the first queue memory is full.
8. The switch of claim 1 , wherein the first queue memory has at least two rows.
9. The switch of claim 8 , wherein the plurality of pointers correspond to a full row of the first queue memory.
10. The switch of claim 8 , wherein the pointers stored in each row of the first queue memory are ordered by position in the row.
11. The switch of claim 1 , wherein the second queue memory comprises dynamic random access memory (DRAM).
12. The switch of claim 11 , wherein the first queue memory comprises static random access memory (SRAM).
13. The switch of claim 11 , wherein the first queue memory comprises DRAM.
14. The switch of claim 1 , wherein the at least one associated egress port is determined for each data packet from a header of the data packet.
15. The switch of claim 1 , further comprising control logic operative to:
write the pointers to the first queue memory;
transfer the plurality of pointers from the first queue memory to the second queue memory; and
dequeue the plurality of pointers from the second queue memory.
16. The switch of claim 15 , wherein:
the first queue memory has at least two rows; and
the control logic writes each pointer to a row of the first queue memory selected dependent on a state of the row.
17. The switch of claim 1 , wherein the plurality of pointers are written to the second queue memory as a packet vector containing the plurality of pointers.
18. The switch of claim 17 , wherein the packet vector forms a linked list in combination with other packet vectors stored in the second queue memory.
19. The switch of claim 18 , wherein the packet vector further contains data indicative of an address of a next packet vector in the second queue memory.
20. The switch of claim 18 , wherein the packet vector further contains data indicative of a number of pointers in the packet vector.