Method and apparatus for sharing internal power supplies in integrated circuit devices
View Patent ↗A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202 - 205 each having internal power supplies is contained in an enclosure 201 . Integrated circuits 202 - 205 are described showing how to make external connection to internal power supplies. Connections 208 - 212 are provided to the internal power supplies of each of devices 202 - 205 . Another embodiment 500 of the system provides for disablement of regulators in multiple integrated circuits 502, 503 , and 504 by another integrated circuit 501 for power consumption reduction. The method FIG. 6 includes providing devices and connecting the internal power supplies together. An integrated circuit 501 with a power supply 400 adapted to the system and method with additional circuitry 308, 404 and 402 for disabling a regulator 306 is described.
1. A multichip package comprising:
a plurality of memory dies,
each memory die comprising an internal supply voltage generator connected to an internal supply voltage terminal, wherein said internal supply voltage terminals of each memory die are connected together within the multichip package.
2. The multichip package as in claim 1 , wherein said memory dies are DRAM dies.
3. The multichip package as in claim 2 , wherein said internal supply voltage generator is a wordline supply voltage generator.
4. The multichip package as in claim 2 , wherein said internal supply voltage generator is a substrate bias supply voltage generator.
5. The multichip package as in claim 1 , wherein said memory dies are flash memory dies.
6. The multichip package as in claim 5 , wherein said flash dies are NAND flash dies.
7. The multichip package as in claim 6 , wherein said internal supply voltage generator is a page program supply voltage generator.
8. The multichip package as in claim 6 , wherein said internal supply voltage generator is a block erase supply voltage generator.
9. A multichip package comprising:
a plurality of memory devices,
each memory device further comprising an internal supply voltage generator connected to an internal supply voltage terminal, wherein said internal supply voltage terminals of each memory device are connected together within the multichip package,
wherein said internal supply voltage generator further comprises:
a regulator connected to a regulator output terminal, a regulator input terminal, and a regulator enable terminal, wherein said regulator enable terminal of said first memory device is connected within the multichip package to a first voltage for enabling said regulator in said first device, and said regulator enable terminal of a second memory device is connected within the multichip package to a second voltage for disabling said regulator in the second device.
10. The multichip package as in claim 9 , wherein said regulator output terminal of the first memory device is connected to said regulator input terminal of a second memory device.
11. A method for constructing a multichip package comprising the steps of:
providing a plurality of memory dies, each memory die having an internal supply voltage generator connected to an internal supply voltage terminal; and
connecting the internal supply voltage terminals of each memory die together within the multichip package.
12. The method for constructing a multichip package as in claim 11 , wherein said memory dies are DRAM dies.
13. The method for constructing a multichip package as in claim 12 , wherein said internal supply voltage generator is a wordline supply voltage generator.
14. The method for constructing a multichip package as in claim 12 , wherein said internal supply voltage generator is a substrate bias supply voltage generator.
15. The method for constructing a multichip package as in claim 11 , wherein said memory dies are flash memory dies.
16. The method for constructing a multichip package as in claim 15 , wherein said flash dies are NAND flash dies.
17. The method for constructing a multichip package as in claim 16 , wherein said internal supply voltage generator is a page program supply voltage generator.
18. The method for constructing a multichip package as in claim 16 , wherein said internal supply voltage generator is a block erase supply voltage generator.
19. A method for constructing a multichip package comprising the steps of:
providing a plurality of memory devices, each memory device having an internal supply voltage generator connected to an internal supply voltage terminal; and
connecting the internal supply voltage terminals of each memory device together within the multichip package,
wherein said internal supply voltage generator further includes a regulator connected to a regulator output terminal, a regulator input terminal, and a regulator enable terminal, comprising the further step of connecting the regulator enable terminal of said first memory device within the multichip package to a first voltage for enabling said regulator in said first device, and connecting the regulator enable terminals of a second memory device within the multichip package to a second voltage for disabling the regulator in the second device.
20. The method for constructing a multichip package as in claim 19 , comprising the further step of connecting the regulator output terminal of the first memory device to the regulator input terminal of the second memory device.
21. An integrated circuit die with an internal power supply adapted for sharing said internal power supply with at least one other integrated circuit die in a common package, the adaption comprising a first external connection to the internal power supply.
22. The integrated circuit die with an internal power supply as in claim 21 , wherein said first external connection is selected from the group of wire bond pads and TSV bumps.
23. An integrated circuit device with an internal power supply adapted for sharing said internal power supply with at least one other integrated circuit device in a common package, the adaption comprising a first external connection to the internal power supply,
further comprising a second connection to said internal power supply having a different potential than said first connection.
24. An integrated circuit device with an internal power supply adapted for sharing said internal power supply with at least one other integrated circuit device in a common package, the adaption comprising a first external connection to the internal power supply, further comprising:
a regulator in said power supply; and
a second connection to said internal power supply for disabling the regulator in another similar integrated circuit.
25. A system comprising:
a plurality of memory dies in a multichip package, each memory die comprising an internal supply voltage generator connected to an internal supply voltage terminal, wherein said internal supply voltage terminals of each memory die are connected together within the multichip package.
26. The system as in claim 23 , wherein said memory dies are DRAM dies.
27. The system as in claim 24 , wherein said internal supply voltage generator is a wordline supply voltage generator.
28. The system as in claim 24 , wherein said internal supply voltage generator is a substrate bias supply voltage generator.
29. The system as in claim 24 , wherein said memory dies are flash memory dies.
30. The system as in claim 27 , wherein said flash dies are NAND flash dies.
31. The system as in claim 28 , wherein said internal supply voltage generator is a page program supply voltage generator.
32. The system as in claim 28 , wherein said internal supply voltage generator is a block erase supply voltage generator.
33. A system comprising:
a plurality of memory devices in a multichip package, each memory device further comprising an internal supply voltage generator connected to an internal supply voltage terminal, wherein said internal supply voltage terminals of each memory device are connected together within the multichip package;
wherein said internal supply voltage generator further comprises:
a regulator connected to a regulator output terminal, a regulator input terminal, and a regulator enable terminal, wherein said regulator enable terminal of said first memory device is connected within the multichip package to a first voltage for enabling said regulator in said first device, and said regulator enable terminal of a second memory device is connected within the multichip package to a second voltage for disabling said regulator in the second device.
34. The system as in claim 33 , wherein said regulator output terminal of the first memory device is connected to said regulator input terminal of the second memory device.