Stacked semiconductor devices including a master device
View Patent ↗A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
1. A non-volatile memory chip comprising:
core chip areas that take up more than eighty percent of an entire chip area of the non-volatile memory chip; and
an additional chip area within which are located circuitries configured to receive, from another non-volatile memory chip, signals and voltages, including a voltage sufficiently high for an erase operation, and
the core chip areas having a more miniaturized process technology as compared to the additional chip area.
2. The non-volatile memory chip as claimed in claim 1 wherein the additional chip area is a Through-Silicon Vias area.
3. The non-volatile memory chip as claimed in claim 1 wherein the non-volatile memory chip lacks a high voltage generator.
4. The non-volatile memory chip as claimed in claim 1 further comprising another additional chip area within which is located slave device test logic that is configured to be driven by a separate device during testing.
5. The non-volatile memory chip as claimed in claim 4 wherein the another additional chip area is located directly adjacent the additional chip area.
6. The non-volatile memory chip as claimed in claim 1 wherein flash memory cells are located within some of the core chip areas.
7. The non-volatile memory chip as claimed in claim 6 wherein the flash memory cells are NAND flash memory cells.
8. The non-volatile memory chip as claimed in claim 1 wherein the core chip areas take up more than ninety percent of the entire chip area of the non-volatile memory chip.
9. A flash memory chip comprising:
core chip areas that take up more than eighty percent of an entire chip area of the non-volatile memory chip, page buffers being located within some of the core chip areas; and
an additional chip area within which are located circuitries configured to receive, from another non-volatile memory chip, signals and voltages, and
the core chip areas having a more miniaturized process technology as compared to the additional chip area.
10. The flash memory chip as claimed in claim 9 wherein NAND flash memory cells are located within more than one of the core chip areas.
11. The flash memory chip as claimed in claim 9 wherein the flash memory chip lacks a high voltage generator.
12. The flash memory chip as claimed in claim 9 wherein the additional chip area is a Through-Silicon Vias area.
13. A method comprising:
stacking at least two semiconductor chips, one of the semiconductor chips being a master memory device and another of the semiconductor chips being a slave memory device, the master memory device being substantially larger dimensioned than the slave memory device;
wiring the stacked semiconductor chips together by Through-Silicon Vias; and
connecting the stacked semiconductor chips to a package printed circuit board by flip chip and bumping.
14. The method as claimed in claim 13 wherein the master and slave memory devices are non-volatile memory devices.
15. The method as claimed in claim 14 wherein the non-volatile memory devices are flash memory devices.
16. The method as claimed in claim 15 wherein the flash memory devices are NAND flash memory devices.
17. The method as claimed in claim 13 wherein during the connecting, the master memory device is positioned substantially adjacent the package printed circuit board.
18. The method as claimed in claim 17 wherein the master and slave memory devices are non-volatile memory devices.
19. The method as claimed in claim 18 wherein the non-volatile memory devices are flash memory devices.
20. The method as claimed in claim 19 wherein the flash memory devices are NAND flash memory devices.