High speed DRAM architecture with uniform access latency
View Patent ↗A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
1. A method of reading data in a Dynamic Random Access Memory (DRAM), the method comprising:
receiving a read command and an address on a first edge of a control signal;
activating a bit line equalization circuit and deactivating a word line enable device on the first edge of the control signal;
activating the word line enable device for selecting a word line according to the address after a first delay from the first edge of the control signal;
activating a sense amplifier coupled to a bit line pair for sensing data in a memory cell coupled to the word line and to the bit line pair after the first delay plus a second delay from the first edge of the control signal; and
deactivating the word line enable device for de-selecting the word line on a second edge of the control signal.
2. The method as claimed in claim 1 further comprising:
deactivating a data bus equalization circuit coupled to a data bus pair after a third delay from the first edge of the control signal.
3. The method as claimed in claim 1 further comprising:
activating a pair of column access devices coupled to the bit line pair and the data bus pair after the first delay plus the second delay plus a fourth delay from the first edge of the control signal.
4. The method as claimed in claim 1 further comprising:
latching data from the data bus pair on the second edge of the control signal.
5. The method as claimed in claim 1 wherein the control signal is a clock signal.
6. The method as claimed in claim 1 wherein the control signal is a strobe signal.
7. The method as claimed in claim 1 wherein the first edge of the control signal is a rising edge.
8. The method as claimed in claim 1 wherein the second edge of the control signal is a rising edge.
9. The method as claimed in claim 1 further comprising:
deactivating the sense amplifier on the first edge of the control signal.
10. The method as claimed in claim 1 further comprising:
deactivating the sense amplifier on the second edge of the control signal.
11. The method as claimed in claim 3 further comprising:
deactivating the pair of column access devices on the first edge of the control signal.
12. The method as claimed in claim 3 further comprising:
deactivating the pair of column access devices on the second edge of the control signal.
13. The method as claimed in claim 4 , wherein latching data includes latching data from the data bus pair and at least one other data bus pair.
14. The method as claimed in claim 13 , further including selecting one of latched data corresponding to the data bus pair and the at least one other data bus pair for outputting.
15. The method as claimed in claim 5 , wherein activating a word line enable device includes generating a timing pulse after the first delay.
16. The method as claimed in claim 15 , wherein generating includes latching the timing pulse after the first delay.
17. The method as claimed in claim 16 , wherein generating includes maintaining the timing pulse during a third edge of the control signal occurring between the first edge and the second edge.
18. The method as claimed in claim 1 , wherein the first edge is a rising edge of the control signal.
19. The method as claimed in claim 1 , wherein the first edge and the second edge have the same polarity.