IP Library Granted Patent US 6,529,031
Granted Patent Utility
US 6,529,031 · Confirmation No. 9404

INTEGRATED CIRCUIT CONFIGURATION FOR TESTING TRANSISTORS, AND A SEMICONDUCTOR WAFER HAVING SUCH A CIRCUIT CONFIGURATION

⬇ PDF
Code Description Pages PDF
2001-06-07 TRNA Transmittal of New Application 1 View
2001-06-07 SPEC Specification 15 View
2001-06-07 CLM Claims 3 View
2001-06-07 ABST Abstract 1 View
2001-06-07 DRW Drawings-only black and white line drawings 2 View
2001-06-07 OATH Oath or Declaration filed 2 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
Patent No.
US 6,529,031
App. No.
09/876,706
Filed
2001-06-07
Granted
2003-03-04
Pub. No.
US20010052789A1
Art Unit
2829
PTA
-127 days