Temperature-dependent refresh cycle for DRAM
View Patent ↗A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a temperature-dependent reference voltage source. A capacitor's first and second terminals are connected respectively to the temperature-independent current source, and the temperature-independent voltage source. The capacitor's first terminal is connected to a first input terminal of a comparator. The comparator's second input is connected to the temperature-dependent reference voltage source. The comparator is configured to output a refresh signal in response to a difference between voltages present at the first and second inputs thereof.
1. A circuit for generating a refresh signal for a memory cell, the circuit comprising:
a temperature-independent current source;
a temperature-independent voltage source;
a temperature-dependent reference voltage source;
a capacitor having
a first terminal connected to the temperature-independent current source, and
a second terminal connected to the temperature-independent voltage source; and
a comparator having
a first input connected to the first terminal of the capacitor; and
a second input connected to the temperature-dependent reference voltage source, the comparator being configured to output the refresh signal in response to a difference between voltages present at the first and second inputs thereof.
2. The circuit of claim 1 , further comprising a switch configured to reset the capacitor.
3. The circuit of claim 2 , wherein the switch is in signal communication with the comparator, and wherein the switch is configured to reset the capacitor in response to outputting of a refresh signal by the comparator.
4. The circuit of claim 1 , wherein the temperature-dependent reference voltage source comprises an impedance converter.
5. The circuit of claim 1 , wherein the temperature-dependent reference voltage source comprises an inverting amplifier configured to amplify a reference voltage potential.
6. The circuit of claim 1 , wherein the temperature-independent voltage source comprises an impedance converted configured to generate a temperature-independent voltage.
7. The circuit of claim 1 , wherein the temperature-dependent reference voltage source is configured to convert a temperature-dependent current into a temperature-dependent voltage.
8. The circuit of claim 7 , further comprising a bandgap circuit for providing the temperature-dependent current to the temperature-dependent voltage source.
9. The circuit of claim 1 , wherein the memory cell comprises a DRAM memory cell.
10. A DRAM memory having a memory cell configured to be refreshed by the refresh signal generated by the circuit of claim 1 .
11. The circuit of claim 1 , wherein the comparator is configured to output the refresh signal when the voltage present at the first input exceeds the temperature dependent reference voltage present at the second input.
12. A method for generating a refresh signal for a memory cell, the method comprising:
setting a temperature-independent voltage at a second terminal of a capacitor;
providing a temperature-independent current at a first terminal of the capacitor;
outputting the refresh signal in response to a difference between the temperature-independent voltage and the temperature-dependent reference voltage.
13. The method of claim 12 , further comprising discharging the capacitor concurrently with outputting the refresh signal.
14. The method of claim 12 , wherein outputting the refresh signal comprises outputting the refresh signal when the temperature-independent voltage exceeds the temperature-dependent reference voltage.
15. A circuit for providing a refresh signal to a memory cell, the circuit comprising:
a temperature-dependent oscillator configured to periodically generate the refresh signal at a frequency that depends on a temperature of the memory cell, the temperature-dependent oscillator including a comparator, the comparator having;
a first input for receiving the signal indicative of the temperature of the memory cell, and
a second input for receiving a temperature independent signal, and
a capacitor configured to provide a signal to the second input of the comparator,
the comparator being configured to generate the refresh signal in response to a difference between the signals presented at the first and second inputs thereof, and
means for providing, to the oscillator, a signal indicative of the temperature of the memory cell.
16. The circuit of claim 15 , wherein the oscillator further comprises a switch connected in parallel with the capacitor, the switch being momentarily closed to reset the capacitor when the comparator outputs the refresh signal.