Memory with data control
View Patent ↗In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.
1. A device comprising:
memory;
a first serial data link to serially input one or more packets into the device;
a first memory device input to input a command strobe signal into the device, the command strobe signal delineating a first packet that is serially inputted into the device at the first serial data link, the first packet including a command, executable by the device, and associated with a write mode of device operation;
a second memory device input to input a data strobe signal into the device, the data strobe signal delineating a second packet that is serially inputted into the device at the first serial data link, the second packet including write data; and
circuitry to store the write data in the memory in response to the command.
2. The device as defined in claim 1 further comprising:
a memory device output to output the command strobe signal from the device.
3. The device as defined in claim 2 further comprising:
a second serial data link to output the first packet from the device while the command strobe signal is output from the device at the memory device output.
4. The device as defined in claim 1 further comprising:
a memory device output to output the data strobe signal from the device.
5. The device as defined in claim 4 further comprising:
a second serial data link to output the second packet from the device while the data strobe signal is outputted from the device at the memory device output.
6. The device as defined in claim 5 , wherein the memory device output and the second serial data link maintain a steady state while the second packet is input into the device via the first serial data link.
7. The device as defined in claim 1 further comprising:
link configuration circuitry to establish a width of the first serial data link.
8. The device as defined in claim 1 further comprising:
a data buffer to buffer the write data before it is stored in the memory.
9. The device as defined in claim 1 , wherein the device enters a write mode in response to executing the command, the write mode configuring the device to receive the second packet into the device via the first serial data link.
10. The device as defined in claim 9 , wherein the one or more packets includes a third packet, and a second command strobe signal is inputted into the device at the first memory device input while the third packet is received at the first serial data link, the third packet including a command that is executed by the device and wherein the device exits the write mode in response to executing the command included in the third packet.
11. The device as defined in claim 9 further comprising:
a data buffer to hold data that is to be stored in the memory; and
circuitry to transfer the write data in the second packet to the data buffer in response to the device being in the write mode.
12. The device as defined in claim 1 , wherein the first packet comprises a device address that is associated with the device, the device address being used to address the first packet to the device.
13. A method comprising:
inputting an activated command strobe signal into a memory device at a first input of the memory device, the activated command strobe signal delineating a first packet that is serially inputted into the memory device at a first serial data link of the memory device, the first packet including a command, executable by the memory device, and associated with a write mode of device operation;
inputting an activated data strobe signal into the memory device at a second input of the memory device, the activated data strobe signal delineating a second packet that is serially inputted into the memory device at the first serial data link, the second packet including write data; and
storing the write data in memory.
14. The method as defined in claim 13 further comprising:
outputting the activated command strobe signal from the memory device at an output of the memory device.
15. The method as defined in claim 14 further comprising:
outputting the first data packet from the memory device at a second serial data link of the memory device while the activated command strobe signal is outputted from the memory device at the output.
16. The method as defined in claim 13 further comprising:
outputting the activated data strobe signal from the memory device at an output of the memory device.
17. The method as defined in claim 16 further comprising:
outputting the second packet from the memory device at a second serial data link of the memory device while the activated command strobe signal is output from the memory device at the output.
18. The method as defined in claim 17 further comprising:
maintaining the output and second serial data link at a steady state while the second packet is input into the memory device via the first serial data link.
19. The method as defined in claim 13 , wherein the data strobe signal is deactivated at the second input to suspend inputting the second packet at the first serial data link.
20. The method as defined in claim 19 , wherein the data strobe signal is reactivated at the second input to resume inputting the second packet at the first serial data link.
21. The device as in claim 1 , wherein the command strobe signal delineates boundaries of a sequence of multiple serially transmitted bits in the first packet; and
wherein the data strobe signal delineates boundaries of a sequence of multiple serially transmitted bits in the second packet.
22. The device as in claim 1 further comprising a clock input to input a clock signal, and wherein the device is a synchronous device.
23. The device as in claim 1 , wherein the first serial data link is a single serial link on which sequential bits in the first packet and sequential bits in the second packet are transmitted.
24. The device as in claim 1 , wherein the first packet is a first multi-bit packet of bits that are serially transmitted over the first serial data link; and
wherein the second packet is a second multi-bit packet of bits that are serially transmitted over the first serial data link.
25. The device as in claim 1 , further comprising a clock input to input a clock signal, and wherein each of the one or more packets is synchronously inputted into the device.
26. The device as in claim 1 further comprising:
a processor to de-serialize, based at least in part on the command strobe signal and the data strobe signal, bits in the first packet and bits in the second packet subsequent to transmission of the first packet and the second packet over the first serial data link.
27. The device as in claim 1 , further comprising an input and output data processing unit to de-serialize the second packet.
28. The device as in claim 1 , wherein the command strobe signal delineates a length of the first packet; and
wherein the data strobe signal delineates a length of the second packet.