Method and apparatus for synchronization of row and column access operations
View Patent ↗A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.
1. A semiconductor memory device on a chip including an array of memory cells associated with a sense amplifier power supply circuit and a plurality of column access devices; and an interface coupled to the array of memory cells, the interface comprising:
first delay circuitry for delaying a wordline timing pulse by a first predetermined delay amount to provide a first delayed wordline timing pulse;
a first enable circuit for providing a sense amplifier enable signal in response to the wordline timing pulse and the first delayed wordline timing pulse;
second delay circuitry for delaying the wordline timing pulse by a second predetermined delay amount to provide a second delayed wordline timing pulse, the second predetermined delay amount being greater than the first predetermined delay amount;
a second enable circuit for providing a column select enable signal in response to the wordline timing pulse and the second delayed wordline timing pulse; and
enabling circuitry configured to enable:
the sense amplifier power supply circuit in response to the sense amplifier enable signal, and
selected ones of the plurality of column access devices in response to the column select enable signal, after the sense amplifier power supply circuit is enabled.
2. The semiconductor memory device on a chip of claim 1 , wherein the memory cells comprise dynamic random access memory.
3. The semiconductor memory device on a chip of claim 1 , wherein the interface comprises a static random access memory interface.
4. The semiconductor memory device on a chip of claim 1 , wherein the wordline timing pulse, the sense amplifier enable signal and column select enable signal are all local with respect to the memory array.
5. The semiconductor memory device on a chip of claim 1 , wherein each of the first and second delay circuitry comprises a delay element.
6. The semiconductor memory device on a chip of claim 5 , wherein the delay element of the second delay circuitry is coupled with the word line timing pulse via the delay element of the first delay circuitry.
7. The semiconductor memory device on a chip of claim 1 , further comprising a plurality of logic circuits for logically combining the column select enable signal with a plurality of column address signals for enabling the selected ones of a plurality of column access devices.
8. The semiconductor memory device on a chip of claim 1 , wherein the first enable circuit comprises a logic circuit configured to logically combine the wordline timing pulse and the first delayed wordline timing pulse to provide the sense amplifier enable signal.
9. The semiconductor memory device on a chip of claim 8 , wherein the second enable circuit comprises a logic circuit configured to logically combine the wordline timing pulse and the second delayed wordline timing pulse to provide the column select enable signal.