Semiconductor memory device with sense amplifier and bitline isolation
View Patent ↗A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.
1. A semiconductor memory device, including:
a memory cell connected to a first bitline and associated with a second bitline;
a sense amplifier, including a first input/output node and a second input/output node; and
an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, wherein the bitline isolation includes:
electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by:
electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node,
the sense amplifier being responsive to receipt of at least one sensing activation signal from a controller to initiate a signal amplification process at the first and second input/output nodes;
the signal amplification process causes the first input/output node to tend towards a first final electric potential and the second input/output node to tend towards a second final electric potential different from the first final electric potential, wherein said electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node is carried out after said amplification process has been initiated but before the second input/output node has reached the second final electric potential.
2. The semiconductor memory device defined in claim 1 , wherein said electrically disconnecting the first bitline from the first input/output node and said electrically disconnecting the second bitline from the second input/output node occur substantially simultaneously.
3. The semiconductor memory device defined in claim 1 , wherein said isolator is further configured to electrically re-connect the second bitline to the second input/output node after the refresh operation is complete.
4. The semiconductor memory device defined in claim 1 , further comprising said controller.
5. The semiconductor memory device defined in claim 4 , wherein said controller is operative to cause the isolator to carry out said bitline isolation in response to detection of a command to perform a refresh operation.
6. The semiconductor memory device defined in claim 1 , wherein said electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node is carried out before said signal amplification process has been initiated.
7. The semiconductor memory device defined in claim 1 , wherein said electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node is carried out before the second input/output node has reached an electrical potential that is three-quarters of the way between the first final electric potential and the second final electric potential.
8. The semiconductor memory device defined in claim 7 , further including a pre-charge circuit configured to pre-charge the first and second input/output nodes to a bitline pre-charge voltage that is between the first final electric potential and the second final electric potential.
9. The semiconductor memory device defined in claim 8 , wherein the bitline pre-charge voltage is midway between the first final electric potential and the second final electric potential.
10. The semiconductor memory device defined in claim 8 , wherein the controller is configured to pre-charge the first and second input/output nodes before sending causing the sense amplifier to initiate the signal amplification process at the first and second input/output nodes.
11. The semiconductor memory device defined in claim 8 , wherein the memory cell includes a transistor connected between the first bitline and a capacitor, the transistor having a gate connected to a wordline activatable by the controller, the controller being configured to activate the wordline after pre-charging the first and second input/output nodes and before causing the sense amplifier to initiate the signal amplification process at the first and second input/output nodes, wherein activation of the wordline causes charge sharing between the capacitor and the first bitline.
12. The semiconductor memory device defined in claim 11 , wherein at the time when the wordline is activated, the first bitline is electrically connected to the first input/output node and the second bitline is electrically connected to the second input/output node.
13. The semiconductor memory device defined in claim 12 , wherein the controller is configured to pre-charge the first and second input/output nodes while the first bitline is electrically connected to the first input/output node and the second bitline is electrically connected to the second input/output node.
14. The semiconductor memory device defined in claim 8 , wherein the at least one sensing activation signal is delivered from the controller to the sense amplifier over a first sensing activation line and a second sensing activation line, and wherein the controller is configured to set the first sensing activation line to the first final electric potential and to set the second sensing activation line to the second final electric potential in order to initiate the signal amplification process at the first and second input/output nodes.
15. The semiconductor memory device defined in claim 14 , wherein the sense amplifier includes a first transistor, a second transistor, a third transistor and a fourth transistor, wherein each transistor has a gate, a source and a drain, wherein the source of the first transistor is connected to the drain of the second transistor, to the gates of the third and fourth transistors and to the first input/output node, wherein the source of the third transistor is connected to the drain of the fourth transistor, to the gates of the first and second transistors and to the second input/output node, wherein the drain of the first transistor is connected to the drain of the third transistor and the first sensing activation line and wherein the source of the second transistor is connected to the source of the fourth transistor and the second sensing activation line.
16. The semiconductor memory device defined in claim 15 , wherein said electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node is carried out after said amplification process has been initiated but before the second input/output node has reached an electrical potential that is midway between the bitline precharge voltage and the second final electric potential.
17. The semiconductor memory device defined in claim 1 , wherein the isolator includes:
a first isolation element responsive to a first control signal to cause the first bitline to be electrically connected to or disconnected from the first input/output node; and
a second isolation element responsive to a second control signal independent of the first control signal to cause the second bitline to be electrically connected to or disconnected from the second input/output node.
18. The semiconductor memory device defined in claim 17 , wherein the first isolation element includes a first transistor and wherein the second isolation element includes a second transistor.
19. The semiconductor memory device defined in claim 18 , wherein the first transistor includes a gate that receives the first control signal and wherein the second transistor includes a gate that receives the second control signal.