Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals
View Patent ↗In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
1. A memory interface circuit comprising:
a clock phase circuit receiving a reference clock signal and providing a plurality of clock phase signals shifted in phase relative to each other, the clock phase circuit comprising a delay locked loop for providing the plurality of clock phase signals; and
a plurality of output circuits, each output circuit receiving:
one of a plurality of single data rate signals, and
the plurality of clock phase signals,
each of the plurality of output circuits providing:
an output signal having bits from the respective one of the plurality of single data rate signals synchronized to the plurality of clock phase signals, and each of the plurality of output circuits having a substantially identical layout.
2. The memory interface circuit as claimed in claim 1 wherein at least one of the plurality of single data rate signals includes address information.
3. The memory interface circuit as claimed in claim 1 wherein at least one of the plurality of single data rate signals includes data information.
4. The memory interface circuit as claimed in claim 1 wherein at least one of the plurality of single data rate signals includes command information.
5. The memory interface circuit as claimed in claim 1 wherein at least two of the plurality of single data rate signals includes command information, and each of the at least two of the plurality of single data rate signal have a same polarity.
6. The memory interface circuit as claimed in claim 1 wherein the number of the plurality of clock phase signals is two and the clock phase signals are shifted by substantially 180 degrees relative to each other.
7. The memory interface circuit as claimed in claim 1 wherein the number of the plurality of clock phase signals is four and the clock phase signals are shifted by substantially 90 degrees relative to each other.
8. A memory interface circuit comprising:
a clock phase circuit receiving a reference clock signal and providing a plurality of clock phase signals shifted in phase relative to each other, the clock phase circuit comprising a delay locked loop for providing the plurality of clock phase signals; and
a plurality of output circuits,
each output circuit receiving:
a high logic state signal,
a low logic state signal, and
the plurality of clock phase signals,
at least two of the plurality of output circuits providing:
a pair of complementary clock signals, and each of the plurality of output circuits having a substantially identical layout.
9. The memory interface circuit as claimed in claim 8 wherein the number of the plurality of clock phase signals is two and the clock phase signals are shifted by substantially 180 degrees relative to each other.
10. The memory interface circuit as claimed in claim 8 wherein the number of the plurality of clock phase signals is four and the clock phase signals are shifted by substantially 90 degrees relative to each other.