Error correction scheme for memory
View Patent ↗An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.
1. A system comprising:
a memory block for storing a data word and a corresponding row parity bit;
a local data input/output (I/O) circuit for coupling the data word between the memory block and global datalines and for providing the corresponding row parity bit; and,
a row parity circuit including
a serial parity chain for receiving the data word from the local data I/O circuit and for providing a parity output corresponding to parity of the data word, and
a sense circuit for receiving the parity output and the corresponding row parity bit, for providing an active local parity fail flag if the parity output and the corresponding row parity bit mismatch.
2. The system of claim 1 , wherein the serial parity chain comprises:
an even parity line driven to a first logic level at one end;
an odd parity line driven to a second logic level at one end; and
the parity output being provided from the other end of the even parity line and the odd parity line.
3. The system of claim 2 , wherein the sense circuit comprises:
a cross-coupled latch for receiving and latching the parity output and providing a latched parity output; and
a comparator circuit for comparing the latched parity output to the corresponding row parity bit.
4. The system of claim 3 , wherein the sense circuit comprises:
switching means for coupling the latched parity output to the memory block during a write operation.
5. The system of claim 1 , wherein the serial parity chain is segmented into at least two serially connected sub-parity circuits.
6. The system of claim 1 , wherein the memory block comprises:
one of redundant rows and columns, and corresponding redundancy circuits.
7. The system of claim 1 , further comprising:
a parity block for storing a column parity word and a corresponding parity block row parity bit, wherein each bit of the column parity word represents a column parity for a corresponding bit position of the data word;
a parity block local data I/O circuit for coupling the column parity word between the parity block and global datalines and for providing the corresponding parity block row parity bit;
a parity block parity circuit including:
a parity block serial parity chain for receiving the column parity word from the parity block local data I/O circuit and for providing a parity block parity output corresponding a parity of the column parity word, and
a parity block sense circuit for receiving the parity block parity output and the corresponding parity block row parity bit, for providing a parity block active local parity fail flag if the parity block parity output and the corresponding parity block row parity bit mismatch; and
a column parity circuit coupled to the local data I/O circuit and the parity block for receiving a parity block data word and the column parity word and for comparing column parity of each bit position of the data word to a corresponding bit of the column parity word in response to the active local parity fail flag, the column parity circuit inverting data of each bit position of the data word that fails column parity.
8. The system of claim 7 , wherein the memory block, the local data I/O circuit, the row parity circuit, the parity block, the parity block local data I/O circuit, and the column parity circuit are integrated in an embedded dynamic random access memory (DRAM).
9. The system of claim 8 , wherein the column parity circuit comprises:
a multiplexor circuit coupled between the local data I/O circuit and the global datalines for receiving the data word and for iteratively providing each bit of the data word to one of the global datalines;
a parity block multiplexor circuit coupled to the parity block data I/O circuit for receiving the bits of the column parity word and for providing one bit of the column parity word in each iteration;
a parity evaluator circuit coupled to the global datalines for receiving the one bit of the column parity word, the parity evaluator circuit comparing parity of the global datalines to the one column parity bit in each iteration and generating an active global parity fail flag in response to column parity failure; and
a global dataline inverting circuit for receiving and inverting data of all the global datalines in response to the active global parity fail flag.
10. The system of claim 9 , wherein the multiplexor circuit and the parity block multiplexor circuit each include a counter.
11. The system of claim 9 , wherein the parity evaluator circuit comprises:
a serial parity chain coupled to the global datalines for providing a parity output corresponding to parity of the global datalines; and
a sense circuit for receiving the parity output and the one bit of the column parity word, for providing the active global parity fail flag if the logic state of the parity output and the logic state of the one bit of the column parity word mismatch.
12. The system of claim 9 , wherein the global dataline inverting circuit comprises:
a flip-flop having an input coupled to one global dataline;
an output coupled to a complementary global dataline of the one global dataline;
a complementary output coupled to the global dataline; and
a clock input for receiving the active global parity fail flag.
13. The system of claim 7 , wherein the parity block has a configuration identical to that of the memory block.
14. The system of claim 1 , further comprising:
a column parity check circuit for selectively inverting bits of a column parity word on the global datalines in a write operation for writing a new word to an address corresponding to the data word stored in the memory block, the column parity check circuit including,
a parity comparison circuit for storing the data word and the new word and for comparing each bit position of the data word to each corresponding bit position of the new word, the parity comparison circuit providing mismatch flag signals corresponding to each bit position having mismatching logic states, and
a parity inverting circuit coupled to the global datalines and for receiving the mismatch flag signals, the parity inverting circuit inverting the logic state of the global datalines having bit positions corresponding to the mismatch flag signals.
15. The system of claim 1 , wherein the memory includes one of dynamic random access memory (DRAM), static random access memory (SRAM), flash, and ferro-electric random access memory (FeRAM).