Flash memory program inhibit scheme
View Patent ↗A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
1. A method for programming a selected memory cell of a NAND string connected to a bitline, the method comprising:
precharging a selected memory cell channel to a primary boosted voltage level when the bitline is biased with a program inhibit voltage by
driving wordlines connected to unselected memory cells of the NAND string to a first pass voltage, and
driving the selected wordline to a second pass voltage, the second pass voltage is less than the first pass voltage, and enables conductivity of the selected memory cell channel during precharging;
decoupling the selected memory cell from the NAND string when a selected wordline connected to the selected memory cell is at a programming voltage level.
2. The method of claim 1 , further including turning on a string select transistor of the NAND string before precharging.
3. The method of claim 2 , wherein turning on includes driving a string select signal connected to the string select transistor to a voltage supply level, and subsequently reducing the string select signal to a leakage minimization voltage during precharging.
4. The method of claim 1 , wherein decoupling includes driving the selected wordline from the first pass voltage to the programming voltage level.
5. The method of claim 1 , wherein decoupling includes electrically turning off at least one of a first transistor device and a second transistor device both adjacent to the selected memory cell.
6. The method of claim 5 , wherein the first transistor device includes a string select transistor of the NAND string connected to the bitline, and the second transistor device includes a lower unselected memory cell between the selected memory cell and a source line connected to the NAND string.
7. The method of claim 6 , wherein the string select transistor is turned off during precharging, and electrically turning off includes driving a wordline connected to the unselected memory cell to a second pass voltage lower than the first pass voltage.
8. The method of claim 5 , wherein the first transistor device includes an upper unselected memory cell between the selected memory cell and the bitline, and the second transistor device includes a lower unselected memory cell between the selected memory cell and a source line connected to the NAND string.
9. The method of claim 8 , wherein electrically turning off includes driving an upper wordline connected to the upper unselected memory cell and a lower wordline connected to the lower unselected memory cell to a third pass voltage lower than the first pass voltage.
10. The method of claim 5 , wherein the first transistor device includes an upper unselected memory cell between the selected memory cell and the bitline, and the second transistor device includes a ground select transistor of the NAND string connected to a source line.
11. The method of claim 10 , wherein the ground select transistor is turned off before precharging, and electrically turning off includes driving an upper wordline connected to the upper unselected memory cell to a third pass voltage lower than the first pass voltage.
12. A method for programming a NAND string coupled to a bitline biased to a programming voltage or a program inhibit voltage, comprising:
driving upper wordlines between a selected wordline and the bitline with a first pass voltage, memory cells of the NAND string connected to the upper wordlines being sufficiently turned on by the first pass voltage to couple the programming voltage or the program inhibit voltage to a selected memory cell connected to the selected wordline;
driving the selected wordline with the first pass voltage to couple a channel of the selected memory cell to the programming voltage when the bitline is biased to the programming voltage, and to precharge the channel of the memory cell to a primary boosted voltage level when the bitline is biased to the program inhibit voltage;
driving lower wordlines between the selected wordline and a source line to a second pass voltage while driving the upper wordlines and driving the selected wordline with the first pass voltage, the second pass voltage is less than first pass voltage and higher than a threshold voltage of a programmed memory cell;
driving the selected wordline with a programming voltage level to program the selected memory cell when the bitline is biased to the programming voltage, and to inhibit programming of the selected memory cell when the bitline is biased to the program inhibit voltage; and
decoupling the selected memory cell from the memory cells connected to the upper wordlines while the selected wordline is driven to the programming voltage level.
13. The method of claim 12 , wherein decoupling includes reducing the second pass voltage of a lower wordline adjacent to the selected wordline to a third voltage while driving the selected wordline with the programming voltage level.
14. The method of claim 13 , wherein the third voltage is lower than the second pass voltage and greater than 0V, a memory cell connected to the lower wordline turning off when the selected wordline is at the programming voltage level.
15. The method of claim 13 , wherein the third voltage is an off voltage for turning off a memory cell connected to the lower wordline when the selected wordline is at the programming voltage level.
16. The method of claim 12 , wherein decoupling includes reducing the first pass voltage of an upper wordline adjacent to the selected wordline to a third pass voltage, the third pass voltage being a voltage level for enabling a memory cell connected to the upper wordline to couple the programming voltage to the selected memory cell.
17. The method of claim 12 , further including turning on a string select transistor of the NAND string before driving the upper wordlines.
18. The method of claim 17 , wherein turning on includes driving a string select signal connected to the string select transistor to a voltage supply level, and subsequently reducing the string select signal to a leakage minimization voltage during driving of the upper wordlines, the leakage minimization voltage being at a voltage level to pass the programming voltage.