Pre-charge voltage generation and power saving modes
View Patent ↗A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
1. An integrated circuit comprising:
a data bus including a plurality of data bus lines;
a voltage generator circuit including:
an input configured to receive an input signal indicating one of a power saving mode and a non-power saving mode of operation of the integrated circuit; and
an output configured to provide a precharge voltage to at least one of the plurality of data bus lines,
the precharge voltage having a first value between a voltage value of a logic high state and a voltage value of logic low state when the input signal indicates that the integrated circuit is in the non-power saving mode of operation; and
the precharge voltage having a second value nearer to one of the voltage value of the logic high state and the voltage value of the logic low state than the first value when the input signal indicates that the integrated circuit is in the power saving mode of operation.
2. The integrated circuit as claimed in claim 1 , wherein the voltage generator circuit includes:
a voltage adjustor circuit configured to receive the input signal and adjust the precharge voltage.
3. The integrated circuit as claimed in claim 2 , wherein the voltage adjustor circuit includes;
at least one field effect transistor configured to electrically couple the output to a higher voltage value than a voltage value of the pre-charge voltage signal as produced by the voltage generator circuit when the memory circuit is in the non-power saving mode of operation.
4. The integrated circuit as claimed in claim 1 further comprising:
a driver circuit configured to drive one or more of the plurality of data bus lines to different logic states.
5. The integrated circuit as claimed in claim 1 further comprising:
a switch circuit configured to selectively couple the output to one or more of the plurality of data bus lines.
6. The integrated circuit as claimed in claim 1 further comprising:
one or more field effect transistors configured to adjust a magnitude of the precharge voltage.
7. The integrated circuit as claimed in claim 1 further comprising:
a driver circuit configured to drive one or more of the plurality of data bus lines to different logic states;
a switch circuit configured to selectively couple the output to one or more of the plurality of data bus lines; and
a current leakage path extending from the driver circuit along the at least one signal through the switch circuit to the voltage generator circuit, the respective switch circuit being oriented in the current leakage path such that a first node of the switch circuit is in electrical communication with the at least one data bus signal and a second node of the switch circuit is in electrical communication with the output.
8. The integrated circuit as claimed in claim 1 further comprising a sense amplifier configured to change the at least one of the plurality of data bus lines to one of the voltage value of the logic high state and the voltage value of the logic low state.
9. The integrated circuit as claimed in claim 1 , wherein a type of the integrated circuit is selected from the group consisting of dynamic random-access memory (DRAM), static random-access memory (SRAM), pseudo-static random-access memory (PSRAM), resistive random-access memory (ReRAM), ferroelectric random-access (FeRAM), NAND Flash memory, NOR Flash memory, electrically erasable read-only memory (EEPROM), magnetoresistive random-access memory (MRAM), and phase change memory (PCM).
10. The integrated circuit as claimed in claim 1 wherein the first value is substantially half way between the voltage value of the logic high state and the voltage value of the logic low state.
11. A method of precharging a data bus signal in an integrated circuit, the method comprising:
receiving an input signal specifying a mode of operation of the integrated circuit;
determining whether the mode of operation is one of a non-power saving mode of operation and a power saving mode of operation;
precharging the data bus signal to a first value between a voltage value of a logic high state and a voltage value of a logic low state when the input signal specifies the integrated circuit is in the non-power saving mode of operation; and
precharging the data bus signal to a second value nearer to one of the voltage value of the logic high state and the voltage value of the logic low state than the first value when input signal indicates that the integrated circuit is in the power saving mode of operation.
12. The method as claimed in claim 11 wherein precharging the data bus signal to the first value includes precharging the data bus signal to a value substantially half way between the voltage value of the logic high state and the voltage value of the logic low state.
13. The method as claimed in claim 11 wherein precharging the data bus signal to the second value nearer to one of the voltage value of the logic high state and the voltage value of the logic low state includes precharging the data bus signal to one of the voltage value of the logic high state and the voltage value of the logic low state.