Flash memory system
View Patent ↗A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
1. A multiple bit per cell (MBC) flash memory system comprising:
an MBC flash memory device comprising:
a plurality of MBC flash memory banks,
a plurality of erasable blocks in each MBC flash memory bank, and
a plurality of physical pages in each erasable block, each physical page configured to store a maximum of N logical pages, N being an integer greater than two, and each of the erasable blocks configured to operate in a plurality of storage modes, the plurality of modes comprising:
a full MBC storage mode for programming all of the N logical pages for each physical page;
a partial MBC storage mode for programming a subset of the N logical pages comprising at least two and less than the N logical pages for each physical page; and
a single bit per cell (SBC) storage mode for programming a single logical page for each physical page; and
a memory controller communicatively coupled to the MBC flash memory device, the memory controller configured to: determine one of the plurality of storage modes for each erasable block of the at least one MBC flash memory device, and issue a page program command packet set comprising at least one page program command packet, the page program command packet set limited to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each physical page of the MBC flash memory device, each page program command packet comprising a row address having at least one bit representing a selected physical page and at least one bit representing a logical page address of the subset of logical page addresses corresponding to the selected physical page when the partial MBC storage mode is determined.
2. The multiple bit per cell (MBC) flash memory system of claim 1 , further comprising a mapping table for storing storage mode information for each of the erasable blocks.
3. The multiple bit per cell (MBC) flash memory system of claim 2 , wherein the memory controller is further configured to populate the mapping table with the storage mode information from the at least one MBC flash memory device during a power up sequence of the multiple bit per cell (MBC) flash memory system.
4. The multiple bit per cell (MBC) flash memory system of claim 3 , wherein the mapping table is comprised in a local memory and configured to include address binding information associated with a determined storage mode for each of the erasable blocks.
5. The multiple bit per cell (MBC) flash memory system of claim 3 , wherein the memory controller includes: control circuitry for accessing the mapping table and providing the page program command packet set based on the determined storage mode information in the mapping table.
6. The multiple bit per cell (MBC) flash memory system of claim 5 , wherein each page program command packet comprises: a page of data, address information for selecting one of the erasable blocks of the MBC flash memory device and a physical page address within the selected erasable block, and a logical page address for the page of data to be programmed in the physical page.
7. The multiple bit per cell (MBC) flash memory system of claim 3 , wherein the memory controller is further configured to store the storage mode information for each of the erasable blocks in the MBC flash memory device using the SBC storage mode.
8. The multiple bit per cell (MBC) flash memory system of claim 1 , wherein for each of the erasable blocks operating in the full MBC storage mode, the page program command packets set comprises N successive page program command packets.
9. The multiple bit per cell (MBC) flash memory system of claim 1 , wherein for each of the erasable blocks operating in the partial MBC storage mode, the page program command packet set consists of M successive page program command packets, wherein M is an integer greater than one but less than N.
10. The multiple bit per cell (MBC) flash memory system of claim 1 , wherein for each of the erasable blocks operating in the SBC storage mode, the page program command packet set consists of a single page program command packet.
11. The multiple bit per cell (MBC) flash memory system of claim 1 , wherein for the full MBC storage mode and the partial MBC storage mode, the logical pages for each physical page are programmed starting from the lowest logical page.
12. The multiple bit per cell (MBC) flash memory system of claim 1 , wherein for the single bit per cell (SBC) storage mode, the lowest logical page is programmed for each physical page.