Non-volatile semiconductor memory device with power-saving feature
View Patent ↗A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.
1. A method comprising:
causing a non-volatile semiconductor memory device to switch from a first operational state to a second operational state in response to recognizing an erase command or a program command received by the non-volatile semiconductor memory device;
electrically connecting a voltage supply terminal of the non-volatile semiconductor memory device to a node of the non-volatile semiconductor memory device when the non-volatile semiconductor memory device is in the first operational state;
electrically decoupling the voltage supply terminal from the node when the non-volatile semiconductor memory device is in the second operational state;
causing the non-volatile semiconductor memory device to switch from the second operational state back to the first operational state; and
issuing a status signal to indicate that the non-volatile semiconductor memory device is ready, after the non-volatile semiconductor memory device is caused to switch back to the first operational state.
2. The method defined in claim 1 , further comprising starting an erase operation, if and after the erase command is recognized.
3. The method defined in claim 2 , wherein the causing of the non-volatile semiconductor memory device to switch from the second operational state back to the first operational state occurs before the erase operation is complete.
4. The method defined in claim 1 , further comprising starting a program operation, if and after the program command is recognized.
5. The method defined in claim 4 , wherein the causing of the non-volatile semiconductor memory device to switch from the second operational state back to the first operational state occurs before the program operation is complete.
6. The method defined in claim 1 , wherein the node leads to a power supply for supplying power to circuitry of the non-volatile semiconductor memory device when the voltage supply terminal is electrically connected to the node.
7. The method defined in claim 6 , wherein prior to switching from the first operational state to the second operational state, a voltage at the voltage supply terminal matches a voltage of the power supply and wherein after switching from the first operational state to the second operational state, the voltage at the voltage supply terminal begins to decrease in absolute value.
8. The method defined in claim 7 , wherein the decrease in absolute value continues until the voltage at the voltage supply terminal stabilizes at around a final level.
9. The method defined in claim 1 , further comprising outputting a signal indicative that the device is busy in further to recognizing the erase command or the program command.
10. The method defined in claim 9 , wherein the outputting of the signal indicative that the device is busy occurs after the causing of the non-volatile semiconductor memory device to switch from the first operational state to the second operational state.
11. The method defined in claim 1 , wherein the non-volatile semiconductor memory device is a NAND flash memory device.
12. The method defined in claim 1 , wherein the non-volatile semiconductor memory device is a NOR flash memory device.
13. The method defined in claim 1 , wherein:
the node is an internal voltage node, and
a first voltage at the internal voltage node is different from a second voltage associated with the voltage supply terminal.
14. The method defined in claim 1 , wherein the node is an internal voltage node.