IP Library Granted Patent US 7,390,686
Granted Patent B2
US 7,390,686 · App. 11/319,587 · Granted Jun 24, 2008

CMOS image sensor and method for fabricating the same

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Quick Facts
Patent No.
US 7,390,686
App. No.
11/319,587
Granted
Jun 24, 2008
Kind
B2
Abstract

A CMOS image sensor and a method for fabricating the same are disclosed, in which light that transmits through a microlens is prevented from being beyond a photodiode region to minimize loss of incident light and to improve low illumination characteristics of the CMOS image sensor. The CMOS image sensor includes a semiconductor substrate including a transistor region and a photodiode region, a gate electrode formed on the semiconductor substrate corresponding to the transistor region, an interlayer dielectric layer formed on an entire surface of the semiconductor substrate including the gate electrode, a microlens formed over the interlayer dielectric layer to condense light, and a metal barrier formed in the interlayer dielectric layer to surround a portion of the interlayer dielectric layer corresponding to the photodiode region and to reflect light in the photodiode region that transmits through the microlens but goes beyond the photodiode region.

Claims (11)

1. A method for fabricating a CMOS image sensor comprising:

forming a gate electrode on a transistor region of a semiconductor substrate including the transistor region and a photodiode region;

forming an interlayer dielectric layer on an entire surface of the semiconductor substrate including the gate electrode;

forming a microlens over the interlayer dielectric layer to condense light; and

forming a metal barrier in the interlayer dielectric layer to surround a portion of the interlayer dielectric layer corresponding to the photodiode region and to reflect light to the photodiode region that transmits through the microlens but goes beyond the photodiode region.

2. The method of claim 1 , further comprising forming a metal line between the interlayer dielectric layer and the microlens, and forming a contact in the interlayer dielectric layer to electrically connect the gate electrode with the metal line.

3. The method of claim 2 , wherein the metal barrier and the contact are formed of the same metal.

4. The method of claim 3 , wherein the metal barrier and the contact are formed of W or Al.

5. The method of claim 3 , wherein the metal barrier and the contact are simultaneously formed.

6. The method of claim 5 , wherein the metal barrier and the contact are simultaneously formed by forming a photoresist pattern on the interlayer dielectric layer, selectively etching the interlayer dielectric layer using the photoresist pattern as a mask to respectively form a metal barrier hole and a contact hole, and respectively forming the metal barrier and the contact in the metal barrier hole and the contact hole.

7. The method of claim 6 , wherein the interlayer dielectric layer is etched by an anisotropic etching process.

Assignments (4)
CHANGE OF NAME Recorded Nov 3, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058793/0748 →
RELEASE OF SECURITY INTEREST Recorded Nov 11, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054385/0435 →
AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2017
From: DONGBU HITEK CO. LTD.; DONGBU ELECTRONICS CO., LTD.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 041330/0143 →