IP Library Granted Patent US 8,063,417
Granted Patent B2
US 8,063,417 · App. 12/772,604 · Granted Nov 22, 2011

Integrated circuit device and method for forming the same

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Quick Facts
Patent No.
US 8,063,417
App. No.
12/772,604
Granted
Nov 22, 2011
Kind
B2
Abstract

In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer. A wiring structure is determined based on a wiring structure equation expressing the relations among a voltage drop in the lines, the area occupied thereby, and a current consumed thereby and on a circuit characteristic equation expressing, when the circuit is subdivided while the ratio between the area of the circuit and a current consumed thereby is held constant, the relation between an area occupied by a circuit resulting from subdivision and a current consumed thereby.

Claims (95)

1. An integrated circuit device having a circuit portion including a plurality of electronic elements, the circuit portion being formed of a plurality of cells, the device comprising:

a plurality of first element voltage supply lines connected to a higher potential terminal of each of the plurality of the cells;

a plurality of second element voltage supply lines connected to a lower potential terminal of each of the plurality of the cells;

a first trunk voltage supply line connected to each of the plurality of first element voltage supply lines;

a second trunk voltage supply line connected to each of the plurality of second element voltage supply lines;

a first branch voltage supply line connected to the first trunk voltage supply line to supply a voltage from the outside to the first trunk voltage supply line;

a second branch voltage supply line connected to the second trunk voltage supply line to supply a voltage from the outside to the second trunk voltage supply line;

a first wiring layer provided above the plurality of the cells to have the first and second element voltage supply lines and the first and second trunk voltage supply lines placed therein; and

at least one upper wiring layer provided above the first wiring layer to have the first and second branch voltage supply lines placed therein, wherein:

the plurality of first element voltage supply lines and the plurality of second element voltage supply lines extend in a first direction,

the first and second trunk voltage supply lines and the first and second branch voltage supply lines extend in a second direction,

the first trunk voltage supply line and the first branch voltage supply lines are provided to overlap and are connected to each other by a plurality of connecting terminals, and

the second trunk voltage supply line and the second branch voltage supply line are provided to overlap and are connected to each other by a plurality of connecting terminals.

2. The device of claim 1 , wherein the at least one upper wiring layer includes a second wiring layer and a third wiring layer provided above the second wiring layer.

3. The device of claim 2 , further comprising

a first chip and a second chip, wherein

the third wiring layer is provided in the second chip,

the third wiring layer includes the first and second branch voltage supply lines, and

the first and second element voltage supply lines and the first and second trunk voltage supply lines in the first wiring layer and the first and second branch voltage supply lines in the third wiring layer are connected to each other by bonding the first and second chips to each other.

4. The device of claim 3 , wherein the second chip serves as a substrate used only for wiring.

5. The device of claim 3 , wherein the second chip serves as a micro substrate.

6. The device of claim 5 , wherein the first chip and the second chip are attached to each other with a micro bump.

7. The device of claim 1 , further comprising

a first chip and a second chip, wherein

the plurality of the cells and the first wiring layer are provided in the first chip, the first branch voltage supply line is provided in the second chip, and

the first trunk voltage supply line and the first branch voltage supply line are connected to each other by bonding the first and second chips to each other.

8. The device of claim 7 , wherein the second chip serves as a substrate used only for wiring.

9. The device of claim 7 , wherein the second chip serves as a micro substrate.

10. The device of claim 9 , wherein the first chip and the second chip are attached to each other with a micro bump.

11. The device of claim 1 , further comprising:

a first chip and a second chip, wherein

the plurality of the cells and the first wiring layer are provided in the first chip,

the second branch voltage supply line is provided in the second chip, and

the second trunk voltage supply line and the second branch voltage supply line are connected to each other by bonding the first and second chips to each other.

12. The device of claim 11 , wherein the second chip serves as a substrate used only for wiring.

13. The device of claim 11 , wherein the second chip serves as a micro substrate.

14. The device of claim 11 , wherein the first chip and the second chip are attached to each other with a micro bump.

15. The device of claim 1 , further comprising:

first and second connecting terminals each provided at a connecting point between the first trunk voltage supply line and the first branch voltage supply line, wherein

the first and second connecting terminals are disposed in spaced apart relation with a given distance or more therebetween.

16. The device of claim 1 , further comprising:

first and second connecting terminals each provided at a connecting point between the second trunk voltage supply line and the second branch voltage supply line, wherein

the first and second connecting terminals are disposed in spaced apart relation with a given distance or more therebetween.

17. The device of claim 1 , wherein the first direction is perpendicular to the second direction.

18. The device of claim 1 , wherein:

the first branch voltage supply line includes a first line extending in the first direction and a second line extending in the second direction, and

the first trunk voltage supply line and the second line of the first branch voltage supply line are provided to overlap and are connected to by the plurality of connecting terminals.

19. An integrated circuit device having a circuit portion including a plurality of electronic elements, the circuit portion being formed of a plurality of cells, the device comprising:

a plurality of first element voltage supply lines connected to a higher potential terminal of each of the plurality of the cells;

a plurality of second element voltage supply lines connected to a lower potential terminal of each of the plurality of the cells;

a first trunk voltage supply line connected to each of the plurality of first element voltage supply lines;

a second trunk voltage supply line connected to each of the plurality of second element voltage supply lines;

a first branch voltage supply line connected to the first trunk voltage supply line to supply a voltage from the outside to the first trunk voltage supply line;

a second branch voltage supply line connected to the second trunk voltage supply line to supply a voltage from the outside to the second trunk voltage supply line;

a first wiring layer provided above the plurality of the cells to have the first and second element voltage supply lines and the first and second trunk voltage supply lines placed therein;

at least one upper wiring layer provided above the first wiring layer to have the first and second branch voltage supply lines placed therein, and

a first chip and a second chip, wherein:

the at least one upper wiring layer includes a second wiring layer and a third wiring layer provided above the second wiring layer,

the third wiring layer is provided in the second chip,

the third wiring layer has the first and second branch voltage supply lines, and

the first and second element voltage supply lines and the first and second trunk voltage supply lines in the first wiring layer and the first and second branch voltage supply lines in the third wiring layer are connected to each other by bonding the first and second chips to each other.

20. The device of claim 19 , wherein the second chip serves as a substrate used only for wiring.

21. The device of claim 19 , wherein the second chip serves as a micro substrate.

22. The device of claim 21 , wherein the first chip and the second chip are attached to each other with a micro bump.

23. An integrated circuit device having a circuit portion including a plurality of electronic elements, the circuit portion being formed of a plurality of cells, the device comprising:

a plurality of first element voltage supply lines connected to a higher potential terminal of each of the plurality of the cells;

a plurality of second element voltage supply lines connected to a lower potential terminal of each of the plurality of the cells;

a first trunk voltage supply line connected to each of the plurality of first element voltage supply lines;

a second trunk voltage supply line connected to each of the plurality of second element voltage supply lines;

a first branch voltage supply line connected to the first trunk voltage supply line to supply a voltage from the outside to the first trunk voltage supply line;

a second branch voltage supply line connected to the second trunk voltage supply line to supply a voltage from the outside to the second trunk voltage supply line;

a first wiring layer provided above the plurality of the cells to have the first and second element voltage supply lines and the first and second trunk voltage supply lines placed therein;

at least one upper wiring layer provided above the first wiring layer to have the first and second branch voltage supply lines placed therein; and

a first chip and a second chip, wherein:

the plurality of the cells and the first wiring layer are provided in the first chip, the first branch voltage supply line is provided in the second chip, and

the first trunk voltage supply line and the first branch voltage supply line are connected to each other by bonding the first and second chips to each other.

24. The device of claim 23 , wherein the second chip serves as a substrate used only for wiring.

25. The device of claim 23 , wherein the second chip serves as a micro substrate.

26. The device of claim 25 , wherein the first chip and the second chip are attached to each other with a micro bump.

27. An integrated circuit device having a circuit portion including a plurality of electronic elements, the circuit portion being formed of a plurality of cells, the device comprising:

a plurality of first element voltage supply lines connected to a higher potential terminal of each of the plurality of the cells;

a plurality of second element voltage supply lines connected to a lower potential terminal of each of the plurality of the cells;

a first trunk voltage supply line connected to each of the plurality of first element voltage supply lines;

a second trunk voltage supply line connected to each of the plurality of second element voltage supply lines;

a first branch voltage supply line connected to the first trunk voltage supply line to supply a voltage from the outside to the first trunk voltage supply line;

a second branch voltage supply line connected to the second trunk voltage supply line to supply a voltage from the outside to the second trunk voltage supply line;

a first wiring layer provided above the plurality of the cells to have the first and second element voltage supply lines and the first and second trunk voltage supply lines placed therein;

at least one upper wiring layer provided above the first wiring layer to have the first and second branch voltage supply lines placed therein, and

a first chip and a second chip, wherein:

the plurality of the cells and the first wiring layer are provided in the first chip,

the second branch voltage supply line is provided in the second chip, and

the second trunk voltage supply line and the second branch voltage supply line are connected to each other by bonding the first and second chips to each other.

28. The device of claim 27 , wherein the second chip serves as a substrate used only for wiring.

29. The device of claim 27 , wherein the second chip serves as a micro substrate.

30. The device of claim 27 , wherein the first chip and the second chip are attached to each other with a micro bump.

Assignments (4)
CHANGE OF NAME Recorded Nov 3, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058793/0720 →
RELEASE OF SECURITY INTEREST Recorded Nov 11, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054384/0581 →
AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2016
From: PANASONIC CORPORATION
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 040393/0332 →