NAND flash memory having multiple cell substrates
View Patent ↗A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
1. A NAND flash memory comprising:
at least first and second well sectors, each of the first and second well sectors including at least one memory block;
a first bitline segment connected to the at least one memory block of the first well sector;
a second bitline segment connected to the at least one memory block of the second well sector; and
isolation circuitry connected between the first bitline segment and second bitline segment, the isolation circuitry configured to:
i)be turned off during at least one memory operation of a plurality of different possible memory operations performable within the NAND flash memory; and
ii)be turned on at certain times other than during the at least one memory operation.
2. The NAND flash memory of claim 1 , wherein the at least one memory operation comprises a read operation, and includes precharging the first bitline segment and the second bitline segment.
3. The NAND flash memory of claim 2 , wherein the precharging includes turning on the isolation circuitry for connecting the first bitline segment to the second bitline segment.
4. The NAND flash memory of claim 3 , wherein the turning on includes selecting an addressed part of the isolation circuitry for turning on in response to a portion of a block address used for selecting a memory block for the read operation.
5. The NAND flash memory of claim 4 , wherein the first bitline segment and the second bitline segment are part of a logical bitline having a page buffer connected at one end of the logical bitline and a precharge circuit connected to another end of the logical bitline.
6. The NAND flash memory of claim 5 , wherein the turning on further includes turning on all parts of the isolation circuitry between the addressed part of the isolation circuitry and the page buffer.
7. The NAND flash memory of claim 1 , wherein when the at least one memory operation is being performed, parts of the isolation circuitry between the addressed isolation device and the precharge circuit are turned off.
8. The NAND flash memory of claim 2 , wherein the at least one memory operation comprises an erase operation, which includes:
selecting the first memory block for erasure in response to a block address;
selecting the first well sector in response to at least a portion of the block address; and,
applying an erase voltage to the first well sector.
9. The NAND flash memory of claim 8 , wherein the selecting the first well sector includes inhibiting application of the erase voltage to the second well sector in response to the at least a portion of the block address.
10. The NAND flash memory of claim 1 , wherein the first bitline segment and the second bitline segment are part of a logical bitline having a page buffer connected at one end of the logical bitline and a precharge circuit connected to another end of the logical bitline.