Circuit for clamping current in a charge pump
View Patent ↗A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
1. A charge pump comprising:
a first capacitor coupled to an output of the charge pump;
a pump up current path comprising a first transistor coupled between a first power supply and a first node, the gate of the first transistor coupled to a first output of said phase detector, and a second transistor coupled between the first node and said first capacitor, the gate of the second transistor coupled to a first bias input;
a pump down current path comprising a third transistor coupled between a second power supply and a second node, the gate of the third transistor coupled to a second output of said phase detector, and a fourth transistor coupled between the second node and the first capacitor, the gate of the fourth transistor coupled to a second bias input;
a first alternate current path coupled between the first intermediate node and said second power supply configured to conduct current for a first period of time when said first transistor is switched to an off state; and
a second alternate current path coupled between the second intermediate node and said first power supply configured to conduct current for a second period of time when said third transistor is switched to an off state,
wherein said first alternate current path further comprises a fifth transistor coupled to the first node and a third node, a sixth transistor coupled to the third node and the second power supply, and a first inverter whose input is coupled to the first output of the phase detector and whose output is coupled to the gate of the fifth transistor, the gate of the sixth transistor coupled to a third bias input,
wherein said second alternate current path further comprises a seventh transistor coupled to the second node and a fourth node, an eighth transistor coupled to the fourth node and said first power supply, and a second inverter whose input is coupled to the second output of the phase detector and whose output is coupled to the seventh transistor, the gate of the eighth transistor coupled to a fourth bias input.
2. The charge pump of claim 1 , wherein the first alternate path comprises a PMOS transistor.
3. The charge pump of claim 1 , wherein the second alternate current path comprises a NMOS transistor.
4. The charge pump of claim 1 , wherein the first alternate current path comprises an inverter and a PMOS transistor driven by the inverter.
5. The charge pump of claim 1 , wherein the second alternate current path comprises an inverter and a NMOS transistor driven by the inverter.
6. The charge pump of claim 1 , wherein the fifth transistor and the sixth transistor are each directly connected to the third node.
7. The charge pump of claim 1 , wherein the seventh transistor and the eighth transistor are each directly connected to the first node.
8. The charge pump of claim 1 , wherein the gate of the second transistor is directly connected to the first bias input.
9. The charge pump of claim 1 , wherein the gate of the fourth transistor is directly connected to the second bias input.