Circuit for clamping current in a charge pump
View Patent ↗A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
1. A charge pump comprising:
a) a capacitor; a first input to connect to a first power supply; a second input to connect to a second power supply having a voltage lower than the first power supply, a two output phase detector; a first bias input to connect to a first bias voltage; and a second bias input to connect to a second bias voltage; and,
b) a pump up current path comprising a first transistor connected between said first input and a first intermediate node the gate connected to the first output of said phase detector, and a second transistor connected between the first intermediate node and said capacitor the gate connected to said first bias input; and,
c) a pump down current path comprising a third transistor connected between said second input and a second intermediate node the gate connected to the second output of said phase detector, and a fourth transistor connected between the second intermediate node and the capacitor the gate connected to said second bias input; and,
d) a first alternate current path connected between the first intermediate node and said second input configured to conduct current for a brief period of time when said first transistor is switched to an off state; and,
e) a second alternate current path connected between the second intermediate node and said first input configured to conduct current for a brief period of time when said third transistor is switched to an off state;
wherein said first alternate current path further comprises a fifth transistor connected to the first intermediate node and a third intermediate node; and, a sixth transistor connected to the third intermediate node and the second input; and, said second alternate current path further comprises a seventh transistor connected to the first intermediate node and a fourth intermediate node; and, an eighth transistor connected to the fourth intermediate node and said first input.
2. A charge pump as in claim 1 , wherein said fifth and sixth transistors are directly connected to the third intermediate node and said seventh and eighth transistors are directly connected to the fourth intermediate node.
3. A charge pump as in claim 1 , wherein said first alternate current path further comprises a first inverter having an input connected to the first output of the phase detector and a second inverter connected to the second output of said phase detector, and said fifth transistor's gate is connected to the first output of said phase detector, said sixth transistor's gate is connected to the output of said first inverter, and, said seventh transistors gate is connected to the second output of said phase detector, and said eighth transistor's gate is connected to the output of said second inverter.
4. A charge pump as in claim 3 , wherein said first, second, seventh, and eighth transistors have a first polarity and said third, fourth, fifth, and sixth transistors have a second polarity opposite the first polarity.
5. A charge pump as in claim 4 wherein said first, second, seventh, and eighth transistors are PMOS transistors and said third, fourth, fifth, and sixth transistors are NMOS transistors.
6. A charge pump as claim 3 , further comprising a first clamp capacitor connected between the output of said first inverter and the third intermediate node, and a second clamp capacitor connected between the output said second inverter and the fourth intermediate node.
7. A charge pump as in claim 6 , wherein said first and second clamp capacitors comprise transistors.
8. A charge pump as in claim 1 , wherein said fifth and sixth transistors each have gates connected to the first output of said phase detector and said seventh and eighth transistors each have gates connected to the second output of said phase detector.
9. A charge pump as in claim 8 , wherein said third, fourth, fifth and eighth transistors have a first polarity and said first, second, sixth and seventh transistors have a second polarity opposite the first polarity.
10. A charge pump as in claim 9 , wherein said first, second, sixth, and seventh transistors are PMOS transistors and said third, fourth, fifth, and eighth transistors are NMOS transistors.