Multipage program scheme for flash memory
View Patent ↗A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline.
1. A NAND flash memory device comprising:
a plurality of I/O ports configured to receive a single multi-page program request from a memory controller, the single multi-page program request comprising at least two iterative command and data input sequences, each command and data input sequence comprising command data, address data and write data;
a ready/busy port configured to output a ready/busy signal indicating a busy status of the NAND flash memory device, the ready/busy signal indicates a busy status in between the at least two iterative command and data input sequences;
a flash memory array comprising NAND type memory cells connected to wordlines and coupled to bitlines, each wordline corresponding to a single physical page comprising M logical pages, M being an integer greater than 1;
bitline access circuitry configured to store M logical pages of data before execution of a single multi-page programming cycle, and bias the bitlines to one of enable and inhibit programming for each of 2 M −1 programming iterations based on a combination of bits corresponding to each bitline from the M logical pages of data during execution of the single multi-page programming cycle, each logical page of data being provided from the write data; and
row circuits configured to drive a selected wordline with different time periods for each of the 2 M −1 programming iterations while the bitlines are biased to enable or inhibit programming based on a combination of logic states of the M logical pages of data, and program the M logical pages of data to a single physical page of memory cells in the single multi-page programming cycle.
2. The NAND flash memory device of claim 1 , wherein the command data includes a data load command.
3. The NAND flash memory device of claim 1 , wherein the command data includes a data end command.
4. The NAND flash memory device of claim 1 , wherein the command data of the last command and data input sequence includes a multi-page program start command.
5. The NAND flash memory device of claim 4 , wherein the ready/busy port is further configured to output a ready/busy signal indicating another busy status after the multi-page program start command.
6. The NAND flash memory device of claim 1 , wherein the address data includes address information for selecting a logical page within the single physical page.
7. The NAND flash memory device of claim 6 , wherein the address data of the first command and data input sequence includes a lower page address within the single physical page.
8. The NAND flash memory device of claim 6 , wherein the address data of the last command and data input sequence includes an upper page address within the single physical page.
9. The NAND flash memory device of claim 1 , wherein the bitline access circuitry includes M data buffers each for storing one of the M logical pages of data.
10. The NAND flash memory device of claim 9 , wherein the bitline access circuitry comprises bitline biasing circuitry configured to bias each of the bitlines to one of enable and inhibit programming based on the combination of bits of the M logical pages of data stored in the M data buffers that correspond to each bitline.
11. The NAND flash memory device of claim 10 , wherein each of the M data buffers comprises data storage circuits configured to store one bit of a logical page of data.
12. The NAND flash memory device of claim 11 , wherein each bit position of the M data buffers comprises:
a data verify decoder configured to receive the bits of the M pages of data stored in the M data buffers that correspond to each bitline; and
inversion circuitry configured to invert the bits in response to selected outputs of the data decoder.
13. The NAND flash memory device of claim 1 , wherein each of the different time periods increases in time for each successive programming iteration.