Scalable memory system
View Patent ↗A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
1. A method for executing concurrent operations in a selected memory device of a memory system having serially connected memory devices, comprising:
receiving a first command;
executing core operations in a first memory bank of the selected memory device in response to the first command;
receiving a second command during execution of core operations in the first memory bank;
executing core operations in a second memory bank of the selected memory device in response to the second command;
receiving a third command for requesting result information from one of the first memory bank and the second memory bank;
outputting a read data packet containing the result information in response to the third command; and,
wherein the first command, the second command and the third command are command packets including a series of bits logically configured to include
a mandatory command field for providing an operation code and a device address,
an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,
an optional data field following the address field for providing write data when the operation code corresponds to the write operation.
2. The method of claim 1 , wherein the result information includes one of status register data and read data.
3. The method of claim 1 , wherein
a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and
a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.
4. The method of claim 3 , wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level.
5. The method of claim 4 , wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge.
6. The method of claim 4 , wherein the second command strobe and data input strobe are separated by at least one data latching clock edge.
7. The method of claim 1 , further including powering up the selected memory device before receiving the first command.
8. The method of claim 7 , wherein the step of powering up includes
asserting a control signal to maintain the selected memory device in a default state prior to a power transition;
transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted;
waiting for a predetermined duration of time to allow the power level to stabilize; and,
de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.
9. The method of claim 8 , wherein the second voltage level is a minimum voltage level for stable circuit operation.
10. The method of claim 8 , wherein the second voltage level is a maximum operating voltage level of a power supply.
11. The method of claim 8 , wherein the first voltage level corresponds to a low power mode operating voltage level of a power supply.
12. The method of claim 8 , wherein the first voltage level corresponds to the absence of a power supply.
13. The method of claim 8 , wherein maintaining the memory device in the default state comprises setting device registers in the memory device to a default value.
14. The method of claim 13 , wherein the device registers include command registers.
15. The method of claim 8 , further comprising the step of performing device initialization upon release of the memory device from the default state.
16. The method of claim 15 , wherein the step of performing device initialization comprises generating device address and device identifier information for the memory device.
17. The method of claim 7 , wherein the step of powering up includes
asserting a control signal at a first time, to maintain the memory device in a default state prior to a power transition;
transitioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted;
waiting for a predetermined duration of time to allow the power level to stabilize; and,
de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.
18. A memory system comprising a plurality of memory devices and a controller for controlling the devices, the memory system being capable of performing the function of powering up a selected memory device before receiving a first command, wherein the function of powering up comprises:
asserting a control signal to maintain the selected memory device in a default state prior to a power transition;
transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted;
waiting for a predetermined duration of time to allow the power level to stabilize; and,
de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.
19. A memory system comprising a plurality of memory devices and a controller for controlling the devices, the memory system being capable of performing the function of powering up a selected memory device before receiving a first command, wherein the function of powering up comprises:
asserting a control signal at a first time, to maintain the memory device in a default state prior to a power transition;
transitioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted;
waiting for a predetermined duration of time to allow the power level to stabilize; and,
de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.